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Single Cycle Timed Loop Clock Deriver

VERSION 4 Published

Created on: Oct 5, 2007 9:51 PM by GerardoG - Last Modified:  Oct 5, 2007 9:52 PM by GerardoG

This piece of IP is useful for making "derived" clocks inside a single-cycle timed loop. See the FPGA Sawtooth Wave IP for an application example.



REQUIREMENTS:
Application Software: LabVIEW FPGA Module 8.5
Downloads:
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