This example decodes convolutional encoded bits using Hard Decision Viterbi Decoding, with the following parameters:
Code rate= 1/2; Constraint length (K)=7; Generator matrix= 171, 133 in octal.
The details of the Viterbi Decoder implemented in this example are as follows:
1. Performs hard decision decoding.
2. Fully parallel architecture, with speed optimization enabled.
3. Traceback length programmable (default= 40).
4. Initial latency= traceback length number of data valid cycles.
5. Maximum clock rate= 25MHz.
6. Supports data rate<= clock rate.
7. Device Utilization Summary:
Number of BUFGMUXs 6 out of 16 37%
Number of External IOBs 371 out of 556 66%
Number of SLICEs 4322 out of 13696 31%
The zip file contains the Viterbi Decoder IP and a PC based convolutional encoder to test the decoder.
REQUIREMENTS:Application Software: LabVIEW Full Development System 8.5
Driver Software: NI-5640R 1.2
Hardware Family: RF,Reconfigurable I/O (RIO)
Addon Software: LabVIEW FPGA Module 8.5
Development Topic: FPGAs