This IP is a part of LabVIEW FPGA RF Communications Library available on NI Labs.

This IP performs decoding on the Reed-Solomon encoded data packets.

The IP specifications are as mentioned below.

• Decodes Reed-Solomon code (255, 239) encoded bits.

• Code word length(n)= 255 symbols

• Data word length(k)=239 symbols

• Parity length(2t)= 16 symbols

• Supports shortened codes.

• Symbol size= 8 bits

• Error correcting capability= 8 symbols

• Field generator polynomial p(x)= x^{8 + x}4 + x^{3 + x}2+ 1

• Code generator polynomial g(x)= (x + a^{0)(x + a}1)(x + a^{2)…(x + a}15);a= 0x02

• Fully synchronous design using a single clock, with speed optimization.

• Maximum clock rate= 51MHz

• The IP handles one symbol(8 bits) per clock cycle and requires a maximum of 850 clock cycles to process a block of n symbols

• Device utilization summary (Xilinx Virtex II Pro P30):

• Number of BUFGMUXs           &nbsp ;     6  out of    16  37%

• Number of External IOBs          371  out of   556  66%

• Number of RAMB16s                  13  out of   136 9%

• Number of SLICEs            & nbsp;   3114  out of 13696  22%

NOTE: The example requires Modulation toolkit to perform Reed-Solomon encoding on the PC.

Please send us your valuable comments as it will help us to improve the IP.