This IP performs digital demodulation of a differentially coded BPSK signal. The specs of this IP are as follows:

1. Corrects frequency offsets upto 50kHz.

2. Corrects symbol timing offsets upto 0.5% of the symbol rate.

3. Implements a 31 tap matched filter with programmable filter coefficient set.

4. Has the ability to demodulate in the presence of doppler shift upto 75kHz at doppler rate <=2kHz/s.

5. Bit error rate= 10^-6 at Eb/N0= 10dB (without any doppler shifts and error control coding schemes).

6. Maximum clock rate= 20MHz.

7. IP requires two samples per symbol (Maximum Symbol rate = 10MS/s).

8. Device utilization summary ( Xilinx Virtex II Pro P30)

Number of BUFGMUXs 6 out of 16 37%
Number of External IOPs 371 out of 556 66%
Number of MULT18X 18s 71 out of 136 52%
Number of SLICEs 3966 out of 13696 28%

Required: Fixed-Point Math Library for LabVIEW FPGA

Please post your comments, feedback, queries so that we can improve the demodulator design.