Lock-in Amplifier is an instrument that can detect the amplitude and phase of sinusoidal signal with known frequency in extremely low signal to noise environment. This example shows how to use LabVIEW FPGA to build a lock-in amplifier on CompactRIO. The following diagram illustrates the principle of Lock-in Amplifier. A Phase Locked Loop (PLL) will lock to the frequency in the reference channel and generate clean sinusoidal wave. It then multiplies the signal in the mixer, modulating the weak sinusoidal wave in signal channel to DC frequency. After a low pass filter, the amplitude and phase of weak sinusoidal wave can be revealed. In this example, PLL, mixer and low pass filter are implemented by LabVIEW FPGA. The performance of FPGA based lock-in amplifier can be summarized below:

For detailed description on the principle of lock-in amplifier, see Principle of Lock in amplifier.pdf in attached file. For detailed description on how to setup the example, including hardware and software requirements, see LIA_IPnet_Readme.pdf in attached file. A simplified version of Lock-in Amplifier is also available on the Xilinx academic SPARTAN 3E XUP Board. Please contact the author for more information. Contact Information: Alex Zheng National Instruments alex.zheng@ni.com