This IP supports a two-edge separation measurement application.  It finds rising edges of two boolean inputs and reports the time difference between the edges in number of clock ticks.

The IP VI first waits for a rising edge on Input0.  Once this edge is detected, it latches the current value of the tick count for later use.  Then, the VI waits for a rising edge on Input1.  As soon as this edge is detected, it takes the current tick count value and subtracts the tick count value from the most recent rising edge of Input0.  This difference is the result of the two-edge measurement, output as a separation value in clock ticks.

The included .zip file has the reusable IP as well as an example program.  The example program simply inputs two boolean controls to the IP and reads the separation measurement output.   This process is repeated in an FPGA single-cycle time loop for precision measurement.