This example demonstrates perform correlated digital generation on a cDAQ module using an internal counter as a sample clock.

Instructions for Running:

1.  Select the Physical Channel to correspond to where your signal is output on the cDAQ device.
2.  Select an internal counter on your cDAQ to generate the sample clock.
3.  Specify the Rate of the output digital pattern.
4.  Enter the digital pattern data.

Block Diagram Steps:

1.  Create a Counter Output channel to produce a Pulse in terms of Frequency.
2.  Use the DAQmx Timing VI (Implicit) to configure the duration of the pulse generation.
3.  Use a DAQmx Task Property Node to query the device and channel used in the Task to be able to determine the internal counter output terminal.
4.  Create an Digital Output Channel.
5.  Use string functions to create the internal counter output terminal (e.g. cDAQ1/Ctr0InternalOutput)
6.  Call the DAQmx (Sample Clock) VI which sets the sample clock rate and the source of the clock.  Additionally, set the sample mode to continuous.
7.  Write the data to the output buffer.
8.  Call the Start VI to start the Digital Output Task.  Note that the digital values will not actually be generated until the sample clock is generated.
9. Call the Start VI to arm the counter and begin the pulse train generation.
10. Loop continuously until the user presses the Stop button. Check for errors every 100ms on both tasks using the Is Task Done? VI.
11.  Call the Clear Task VI to clear the Digital Output Task
12.  Call the Clear Task VI to clear the Counter Output Task
13.  Report any errors that may have occurred.

I/O Connections Overview:

Make sure your signal output terminal matches the Physical Channel I/O Control.  For further connection information, refer to your hardware reference manual.