This block of code delays the rising edge of a digital signal by a controllable number of loop iterations.  The code was developed for a motion control algorithm to delay the rising edge of PWM signals sent to a FET or IGBT bridge.  This in turn prevents shoot-through and protects the circuit from current spikes.

The image blow  shows the output of a normal PWM block compared to the output of a PWM block that is delayed.  The PWM signal has an "on" time of 200 iterations, an"off" time of 800 iterations and a rising edge delay of 40 iterations.  When implemented in the control code for a bridge, the required rise delay is a function of the impedance and capacitance of the circuit as well as the dynamics of the FET or IGBT being used.

The inputs to the block are the digital signal (a boolean) and the number of iterations that the rising edge should be delayed.  The output is the dealyed digital signal (a boolean).