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PXI-6653/PXI-6652 NI-Sync ClkOut Loop Back Test

VERSION 1

Created on: Apr 22, 2009 2:31 PM by Ryan_F - Last Modified:  Apr 22, 2009 2:46 PM by Ryan_F

This example demonstrates how to use NI-Sync, along with a Timing & Synchronization board (PXI-6652 or PXI-6653) to route a clock to the ClkOut terminal. The clock signal's frequency is then mwasured on PFI0. This program confirms that the ClkOut signal is present and that its gain is enabled.

 

Language: English

Data of Last update: 04/22/2009

 

Hardware Needed:

PXI Chassis

PXI-6652 or PXI-6653 Timing & Sync Board

Software Needed:

LabVIEW 8.5.1 or Newer

NI-Sync 3.0 or Newer

 

External Connections:

An SMB cable must be connected from the ClkOut terminal to the PFI0 terminal.

 

Steps for Using:

1. Select the Timing & Synchronization board you are using. Make sure that the board is in the timing slot of the PXI chassis (slot 2).

2. Select a Clock Source for export.

4. Select the destination terminal as ClkOut

5. Run the program.

NOTE: Notice that no clock signal is present on PFI0.

6. Press the ClkOut button.

7. The 10 MHz clock is now present on PFI0, confirming its output.

 

syncblock.JPG

 

Downloads:
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TylerC TylerC  says:

Very nice!

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