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Eight Bit Register CLIP Node

VERSION 2

Created on: Apr 24, 2009 2:37 PM by CaptainKirby - Last Modified:  Apr 24, 2009 3:51 PM by CaptainKirby

Functional Description

This is a simple set of VHDL files that can be used to demonstrate CLIP declaration and instantiation. A 1 bit D Latch and a 1 bit and gate are combined together into a simple 8 bit register. Each of the VHDL files includes a corresponding XML description file necessary for CLIP declaration. You can create a CLIP node of the latch or gate, or combine all of the VHDL files together to create the 8 bit register.

 

RegisterVHDL.png

RegisterNode.png

 

Caveats and Additional Notes

The gate and latch are purely combinational logic and do not require any clock. The register requires a clock input to synchronize the register.

 

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Tags: clip, example, xml, component_level_intellectual_property, rio, d_latch, labview, vhdl, register, labview_fpga, compactrio, r_series
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