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FPGA Configure (Change) Sample Rate in Timed Loop

VERSION 3

Created on: Jun 12, 2009 11:35 AM by A_Patel - Last Modified:  Sep 12, 2009 8:11 AM by A_Patel

Functional Description

The FPGA Timed Loop is set to run at 40 mHz. This value cannot be configured. If you need to use a timed loop to sample at a differant rate, you must count each iteration and take a sample at the appropriate iteration.

 

FPGA Configurable Sample Rate.jpg

 

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Tags: fpga, configure, sample, rate, timed, example, change, in, loop, labview-8.6, example, labview-9.0
Average User Rating
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Comments (1)
Oct 19, 2009 4:36 PM
JLS JLS  says:

Simple, clear, and concise - thanks!

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