It is very common when writing G code for an FPGA circuit that you will never need to change from the default number of sync registers on an IO Node, and therefore LabVIEW FPGA has reduced the visibility of these sync registers. However, if you are using CLIPs to bring external IP into LabVIEW FPGA you are required to have an understanding of synchronization registers to be successful in getting the external IP working in your circuit. Not knowing about the current values of sync registers could lead to timing issues.
This tool will place labels on every IO Node in a VI so that a developer can quickly view all of the timing and synchronization registers in their circuit without having to individually open each IO Node's property page.
LabVIEW 2009, LabVIEW FPGA 2009, NI-RIO 3.3