Half-Bridge Control

[Ben_B]

This block of FPGA code can be used to directly control the digital switches (either FETs or IGBTs) in a half-bridge. The block uses a center-aligned PWM generator and a rising edge delay block to generate digital outputs for the high-side and low-side FETs in a half-bridge. Two of these blocks can be used in parallel to create an H-bridge controller for a brushed DC motor, or three of these blocks can be used in parallel to control a brushless DC motor.

The block takes the inputs of PWM period, number of "high" iterations of the PWM signal (which defines the duty cycle), and a number of iterations to delay the rising edge of the FET signals. The outputs of the block are digital signals for the high-side and low-side FETs.

An example pictured below shows the implementation of this half-bridge control in a single-cycle timed loop. The block requires two subVIs, "Center-Aligned PWM Out - SCTL.vi" and "rising edge delay.vi."

[saeedjahdi]

Many Thanks!