LabVIEW FPGA Compile Report can be unclear

[Terry_ALE]

Both resource and timing reports can be hard to read.

Timing shows clocks that may not appear as SCTLs.

Resources show items which are not easy to trace back the resources on the FPGA itself.

This varies based on the target being compiled, for say 7976 (Kintex-7), 5785 (Ultrascale), and x410 (RFSoC).

There could be a knowledgebase article on "How to understanding LabVIEW FPGA compile results"

I know that for more detailed compile results we have exported to Vivado but for new users this can be very intimidating and a big distraction.