DMA Buffer size when interfacing with FPGA

[Intaris]

I'm looking to write a host-based (Windows PC) software to integrate tightly with some FPGA code. I have a mock UI which duplicates the UI of the FPGA VI for quick debugging access. This allows us to store "old" bitfiles and deploy and test even if the FPGA source code has changed.

Windows PC <-> PXI-E Controller <-> FPGA card

I now want to add a DMA channel and my question is the following:

On a RT system (i.e. PXIE-controller in the same chassis as the FPGA card) we would configure the DMA buffer. The data would be transferred from FPGA to RT buffer in the background at a sufficient rate to require only a small transfer buffer on the FPGA. On the RT target, this all makes sense.

If I do the same thing, but on a windows PC interfacing with the FPGA "directly" (Yeah, it's still actually going through the RT) is this buffer being configured still on the RT or is it on the Windows PC?

I'm assuming it's setting the buffer on the RT. i.e. the buffer actually exists int he RAM of my PXI-E controller, not my windows PC? The windows-based FPGA interface is basically a proxy for the RT driver i would assume.

[ZYOng]

---

@Intaris wrote:

If I do the same thing, but on a windows PC interfacing with the FPGA "directly" (Yeah, it's still actually going through the RT) is this buffer being configured still on the RT or is it on the Windows PC?

I'm assuming it's setting the buffer on the RT. i.e. the buffer actually exists int he RAM of my PXI-E controller, not my windows PC? The windows-based FPGA interface is basically a proxy for the RT driver i would assume.

---

I am not entirely sure but I guess the buffer will be on the Windows host.

One thing for sure is that you will have less throughput and more jitter due to network communication. Reference: Is There a Difference in How I Reference My FPGA Target?