LabVIEW FPGA - Single SCTL vs using multiple SCTLs with same clock

[binarystar105]

I'm using LabVIEW FPGA to program a RIO device. I have a producer SCTL that pumps some data in a target-scoped FIFO to be processed in consumer SCTL running at the same clock as that of the producer loop. 

In the consumer loop, I need to perform multiple operations on the data that are not dependent on each other. In order to meet loop timing constraint, I intend to divide my operations in multiple SCTLs (one operation in each loop) and supply the data to each loop separately by creating multiple target-scoped FIFOs in the producer loop with same data written to all of them. All SCTLs will be running at the same clock rate. 

Is putting the code for multiple independent operations in one SCTL different than splitting operations and putting them in to multiple SCTLs all running at same clock? Would that help in meeting timing constraint? Since the critical path would be same in both cases. 

[Terry_ALE]

---

@binarystar105 wrote:

I'm using LabVIEW FPGA to program a RIO device. I have a producer SCTL that pumps some data in a target-scoped FIFO to be processed in consumer SCTL running at the same clock as that of the producer loop. 

In the consumer loop, I need to perform multiple operations on the data that are not dependent on each other. In order to meet loop timing constraint, I intend to divide my operations in multiple SCTLs (one operation in each loop) and supply the data to each loop separately by creating multiple target-scoped FIFOs in the producer loop with same data written to all of them. All SCTLs will be running at the same clock rate. 

Is putting the code for multiple independent operations in one SCTL different than splitting operations and putting them in to multiple SCTLs all running at same clock? Would that help in meeting timing constraint? Since the critical path would be same in both cases. 

---

This will not save anything.  If anything, it will create an issue in case you need to share data between the two loops.  If you need to share data between loops, you need to make FIFOs or something like that.  In the same loop it is just a wire.