Multiple RT Loops; One FPGA Reference

[Jeremy.Stevens]

I have three loops all using the same FPGA reference.

Loop 1 - Reads most of the data from the FPGA for display on the HMI

Loop 2 - Uses the information made available by Loop 1 as well as some additional data read from the FPGA to perform functions needed by the HMI and writes commands to the FPGA.

Loop 3 - Uses Data from Loop1 as well as additional data read from the FPGA to perform safety fuctions and writes commands to the FPGA.

My questions are:

Does the FPGA Refence point to a single memory block where all three loops are looking at the same data?

Do I need shift registers on the While Loops to keep the data updated properly?

Do I need to run all three wires to a Close FPGA Reference from the While Loops to close the reference properly?

[RavensFan · Accepted solution]

Yes.  No.  No.

I assume you mean by the FPGA reference you are talking about the FPGA reference wire going into a node that reads or write to the front panel control or indicator that is part of the VI running on the FPGA.

[Jeremy.Stevens]

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I assume you mean by the FPGA reference you are talking about the FPGA reference wire going into a node that reads or write to the front panel control or indicator that is part of the VI running on the FPGA.

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That is correct. The wire from the Open FPGA VI Reference node at the beginning of the program.

I was pretty sure this was the case. I just wanted to get a second opinion. I really don't like working off assumptions.

Thank you.

[RavensFan]

What you are describing is exactly what I am doing in my VI that communicates with the FPGA VI.  The only thing I'm not doing is accessing the same FPGA front panel item in mulitple places.  But I am accessing different front panel items in different loops.

[Jeremy.Stevens]

I'm trying to be very careful about accessing the FPGA. If the data is available on the RT side, I'm using that data through local variables. The only time Loops 2 and 3 are reading data from the FPGA is when it is not already available from one of the other loops (usually Loop 1). Loop 1 does not write to the FPGA at all.

Loop 2 is event based. It waits for HMI interaction, or changes in data in Loop 1. Using shift registers in Loop 1, the previous itereations' data is compared to the current iteration. A change in data generates an event in Loop 2 (not used for analog signals)

Loop 3 handles my analog signals (pressures and fluid levels) and triggers safety protocols on the FPGA if something goes awry.