The PWM read function from the IPnet PWM example reads high period and low period in series and updates outputs each time. But it has to be synchronized with the period. The output has to be updated after a complete period (high pulse and low pulse).
Otherwise the VI can read wrong information in case of changing duty cycle (read VI reads every 2nd time a wrong combination of high time and low time -> between two PWM periods).
I fixed the bug in the PWM read VI and made an add-on, that you can choose (for input and output VI) where the period starts (with high pulse or low pulse).
In the attachment you will find the both changed FPGA VI´s (written in LabVIEW 2009).
regards
Benni
