Sync a FGEN, HSDIO and M-Series card with a Timing and Sync Card Using LabVIEW with DAQmx

[Adam G]

Overview

This LabVIEW example utilizes this platform to synchronize multiple signal generating modules.

Description
This LabVIEW example shows how to synchronize a FGEN, HSDIO, and M-Series/X-Series modules by using a system timing and control module such as the PXI-6653. This example is useful if you are using two odd sample rates where two clock rates are needed for your application. This example uses the Timing module to override the chassis’ 10 MHz backplane clock and to create a DDS clock for the DAQ module. The FGEN and HSDIO modules are PLL by the backplane clock and all three devices begin generation once they receive the software trigger from the timing module.

Requirements

• Software

LabVIEW 2012 (or compatible)

NI-Sync 12.0 (or compatible)

NI-FGEN 12.0 (or compatible)

NI-HSDIO 12.0 (or compatible)

NI-DAQmx 12.0 (or compatible)

• Hardware

PXI Chassis and Controller (e.g. PXI-1085 & PXI-8119)

Timing and Synchronization Module (e.g. PXI-6653)

Arbitrary Waveform Generator (e.g. PXI-5422)

High Speed Digital I/O Module (e.g. PXI-6556)

M Series/X-Series Device (e.g. PXI-6356)

Steps to Implement or Execute Code

• Select the Timing, HSDIO, FGEN, and DAQ modules resource name.
• Specify the DAQ's input terminal for the external sample clock source.
• Wire the Timing module's DDS Clock Destination terminal (Clk Out) to the DAQ's external sample clock input terminal.
• Run the VI.
• Toggle the Start Trigger control.
• Click the Stop control to end all sessions.

Additional Information or References
VI Snippet

**This document has been updated to meet the current required format for the NI Code Exchange.**