NI VeriStand Add-Ons Documents

Devin_K · ‎10-28-2011

This Add-On is deprecated and is no longer updated with new features or bug fixes. Therefore, it is not recommended for use in new projects. A next-generation engine simulation toolkit is available at: NI Engine Simulation Toolkit for NI VeriStand. The new toolkit offers vast improvements to FPGA space utilization, RT performance, and many new features.

NI VeriStand Add-on: Engine Simulation Custom Device

Overview

The Engine Simulation add-on allows users to test ECUs by simulating an engine. This includes generating cam and crank signals and capturing output events (such as those for fuel injectors and ignition coils).

Instructions for Use

After installing the Engine Simulation add-on, it can be added to a system definition as a custom device. When you add the custom device, you will be prompted to select an FPGA bitfile which contains your engine simulation components. This bitfile can either be one that you have already added to your System Definition in the "Hardware\Chassis\FPGA" section, or you can browse to a bitfile on disk. All available engine components defined in your bitfile will be added to your system definition. Click on the item pages beneath the "Crank and Cams" section and follow the instructions on the page to define your output signals. While running, output signals will be generated based on the value of the "Engine Speed" channel.

Getting Started - Creating and Adding an FPGA

Install all of the software in the "Add-On Requirements" section below.
If you want other IO and Engine simulation: Run the NI VeriStand FPGA Project Wizard to create a new FPGA project with the NI VeriStand template and FPGA I/O that you intend to use (see the documentation for the NI VeriStand FPGA-Based I/O Interface Tools for more information).
If you just want engine simulation: Create a new LabVIEW project and add your FPGA target, its IO and a blank FPGA VI to start from.
Open the FPGA VI, go to the block diagram, and drop the palette item "NI VeriStand FPGA Support >> RIO Library >> Custom Device Components >> Engine Simulation >> Engine Simulation Component.vit" onto the block diagram. The contents of the template VI will be placed on the diagram which inlcudes the angle processing unit, a crank generation loop, a cam generation loop with four cams, eight injector measurements, and eight spark measurements.
Either edit the names of your FPGA I/O in your project to match the names of the I/O in the FPGA VI (For example, change DIO1 to Cam1DigitalOut).
Or click the FPGA I/O nodes in the FPGA VI to change the I/O binding to something valid for your project (For example, change Cam1DigitalOut to DIO1).
If you want other IO and Engine simulation: Customize the FPGA to provide the I/O you desire through the NI VeriStand interface.
If you just want engine simulation: Skip this step
If you want other IO and Engine simulation: Compile the FPGA and Modify the XML to define the data going through the NI VeriStand interface (see the documentation for the NI VeriStand FPGA-Based I/O Interface Tools for more information).
If you just want engine simulation: Compile the FPGA
If you want other IO and Engine simulation: Add the FPGA to the NI VeriStand System Definition in the FPGA category.
If you just want engine simulation: Skip this step
Add the Engine Simulation custom device to the NI VeriStand System Definition.
If you want other IO and Engine simulation: Select the RIO# in the drop down box of the FPGA you just added to the system definition in step 8.
If you just want engine simulation: Browse to the bitfile on disk.
Configure the Engine Simulation custom device as needed.

FPGA Modification and Customization

When configuring the Engine Simulation Custom Device, it parses the provided FPGA bitfile and looks for the following five component types:

Angle Processing Unit Loop
N Teeth M Missing Simulation Loop(s) - typically for Crank signals
Fully Custom Simulation Loop(s) - typically for Cam signals
ECU Event Loop(s) - typically for fuel injectors and ignition coils
Data Replay Loop(s) - for replaying data captured in a data file like VR sensor data

In order to be recognized as a valid engine simulation bitfile, the Angle Processing Loop is required to be present. All other components are optional. In order for components to be recognized, the relevant controls and indicators must be named appropriately. The general form for the name of controls and indicators (except data replay, which uses a different format) are:

<Component Type>: The type of the component. This will be either "APU", "NTeeth", "FullyCustomTeeth", or "ECUEvent"

<Component Name>: The desired name for the component which shows up in the NI VeriStand configuration tree. Examples: "Crank", "Cams", "FI 1", "IC 1", etc...

<Sub-Component Name>: The desired name for the sub-component. This is currently only used for the "FullyCustomTeeth" component type.

<Parameter Name>: The name of the parameter. Each parameter has a different function. See the documentation for the Automotive Engine Simulation (AES) Library for HIL for more information.

All controls and indicators will have a <Component Type> and <Parameter Name>. The component type determines whether a <Component Name> and <Sub-Component Name> are required (see below).