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Power Electronics Development Center
NI Single-Board RIO General Purpose Inverter Controller (GPIC) - Factsheet
Hi Ceslav,
Sorry for the slow response; it's been hectic.
First, consider using a different type of I/O for your application. If you need > 20 MHz speed digital outputs, please use the FPGA Expansion I/O connector (J2). This is a 34-pin, 0.1” ribbon cable connector that gives you 16 unbuffered 3.3 V digital I/O lines (bi-directional) from the Spartan-6 FPGA. Since these are raw, unbuffered and unprotected FPGA IOB signals, you can achieve the maximum speed of the FPGA. The base clock of the Spartan-6 LX 45 is 40 MHz, but you can create derived clocks at faster rates such as 200 MHz. Then create a Single Cycle Timed Loop (SCTL) in LabVIEW FPGA, time it with your derived clock, and place your digital I/O nodes for the expansion I/O signals in the SCTL. Keep in mind that the impedance of ribbon cables is typically 100 Ohms, so you need to consider the length of the cable and termination at the receiving end of the signal. On your receiving board, use traces that have 55 Ohm impedance so that it is matched for best signal integrity. Then you can achieve rise/fall times in the range of a few nanoseconds. Also, you need to be very careful when using the Expansion I/O signals since they are raw, unbuffered, unprotected FPGA input/output buffer (IOB) lines. But for speed, they cannot be beat. Typical uses for the expansion I/O include gate command signals for high frequency MOSFET (and SiC) DC-to-DC converters (switching frequencies > 100 kHz), FPGA-to-FPGA communication, fiber optic transceivers, SPI/I2C sensor interfaces, GPS signals, etc.
Coming back to the high speed digital outputs now… The 12 High Speed DO (HSDO) section outputs are designed to provide the push/pull type output for controlling external gate driver circuits. Since the range is 24 Vdc, a 10 ns rise/fall time for the HSDO output drivers is actually extremely fast when you consider the entire signal chain. Think of the HSDO outputs as a MOSFET half-bridge that either pulls up hard to Vext or down hard to GND.
The output termination for the HSDO is an area for which we need feedback from the community. Our preference is to include a 100 Ohm series termination resistor on the GPIC; this will ensure good signal integrity from the GPIC, across a ribbon cable to the gate driver, but it does slow down the slew rate considerably for the use case of a SEMIKRON SKiiP 3 IPM. In that case, because of the low impedance of the SKiiP 3 IPM driver, you can expect a rise/fall time of 500 ns for 24 Vdc or 250 ns for 12 Vdc (the logic threshold for SKiiP 3). Take for example a connection circuit schematic shown below.
With the 100 Ohm series resistor on the HS DO, the waveforms are well behaved- overshoot and ringing is eliminated and cross talk to adjacent HSDO signals is low. See the simulated and actual measurements below. Note: The slower rise time can be compensated for digitally in the FPGA in the digital PWM generation algorithm. If you know the delay, you can send the gate command signal early to effectively eliminate it. At a constant temperature, the delay will be relatively constant (perhaps only a few nanoseconds of variation).
On the contrary, if we eliminate the 100 Ohm series resistor, you will have to design an impedance matching AC termination scheme to avoid significant overshoot and ringing.
The push-pull driver circuit of the HSDO has a rise/fall time of ~10 ns. These signals propagate through relatively long ribbon cables that have a characteristic impedance of 60 to 100 Ω. Unless the proper termination scheme is used, impedance mismatch between driver, cable and receiver will induce reflections. These reflections will lead to voltage overshoot and ringing that can cause a variety of problems, including damage to receiver electronics, radiated emissions that could impact other signals, and reflections that degrade the timing certainty of switching instant and reliability. To make it clear, below I'm showing the same circuit without a 100 Ohm series resistance included on the GPIC HSDO.
As you can see, that type of ringing is completely unacceptable. You can see that the low impedance of the 1 nF capacitor on the SKiiP Driver inputs is the main cause of the problem. That's much larger than you would see on a typical CMOS Receiver, which typically has a 5 pF input capacitance. For applications that need a rise/fall time of 10 ns, it can still be achieved with the 100 Ohm series resistor as long as your receiver circuit has a high impedance. The circuit and simulation waveforms are shown below.
The rise/fall time of 10 ns is preserved and the signal integrity will be good. However, due to the very fast edge rate on the cable, cross talk and radiated energy could be a challenge.
Therefore, my opinion is that we should include the 100 Ohm series termination resistor. Any objections?
Are there any applications that absolutely demand that the HSDO output have 0 Ω output impedance?
Here is what it would like like in that case, with the requirement that you provide your own AC termination scheme such as the 100 Ω/100 pF termination shown below. I worry about asking every customer to create their own AC termination scheme like this. But... we definitely want feedback if this is what someone would like us to remove the 100 Ohm series resistor. Doing so would also significantly increase the current drive capabilities of the HSDO; likely to around 0.5 A/channel.
Big thanks to the NI R&D engineers that provided these simulations and measurements to help us all understand the tradeoffs.
Please share your thoughts and opinions, or just reply with a vote; either:
- YES: Include the 100 Ohm series resistor on HSDO, or
- NO: Do not include the 100 Ohm series resistor on HSDO
