Fast RF Power Diagnostics for the DIII-D Fast Wave Current Drive System using FlexRIO

[ChristophW]

Fast RF Power Diagnostics for the DIII-D Fast Wave Current Drive System Using Commercial FPGA Based Systems

B. Runnels2, T. Debelle2, E. Fredd4, N. Greenough4, A. Horton3, R. Marawar2, A. Nagy1, R.I. Pinsker1, J. Rachniowski2, A.Veeramani2, C. Wimmer2

1General Atomics, San Diego, CA 92121

2National Instruments, Austin, TX 78759

3Oak Ridge National Laboratory, TN 37831

4Princeton Plasma Physics Laboratory, Princeton, NJ 08543

The Fast Wave Current Drive System is used to heat and drive non-inductive current in the DIII-D tokamak plasma. The phase and power of the transmitted and reflectedRF wave transferred to the antenna are measured at different points in the transmission lines. These measurements are extremely critical to help tune the system to transfer maximum power to the plasma and to provide fast interlocks to protect the transmitter and the transmission line. Currently there are two systems at DIII-D to perform these functions. One system is used for measuring amplitude and phase of the RF signals for initial tuning of the transmission line before start-up and during plasma shots. The second system is used for arc protection. While this system worked well, it was expensive to maintain

and offered only fixed functionality. Furthermore, a higher sampling speed would allow higher resolution of the data used for post-shot analysis. Additionally a microsecond level interlock system could have an improved response time. The National Instruments FPGA-based FlexRIO board, digitizer module, and PXI Express platform were chosen to perform both high-accuracy measurements and for interlocks. This commercially available system offers faster ADCs and an on-board FPGA to perform real-time signal processing without suffering the latency of sending the data to a CPU. This allowed

the system to achieve microsecond-scale response time and provides the ability for the users to modify the functionality through the user programmable FPGA. This paper will detail the system architecture, performance comparison between the original and new systems, and preliminary testing of the interlock system.