Acquire and 'bit-pack' multiple boolean values on LV FPGA

[StephenB]

Overview

This example demonstrates how to bit-pack multiple boolean values into one unsigned integer on FPGA

Description

When acquiring a digital waveform in LabVIEW FPGA, the return type is a bool. DMA FIFO transfers from target to host are 32 bit width at the lowest level regardless of how the FIFO is configured (bool, U8, etc). So if you intend to do DMA FIFO transfer of a digital waveform from target to host, if you configure the DMA FIFO to be of type bool, the FIFO is then incredibly inefficient (1/32 efficiency). Additionally, when the bool gets to the host, the host stores bools in memory as a whole byte instead of just a bit (1/8 efficiency).

By packing the digital reads into a U32 on the FPGA level before transferring them up to the host, you avoid the inefficiency of a DMA FIFO configured with the bool data type. You also avoid the inefficiency of storing bools in your host side memory as full bytes.

Finally, because you are sending U32s up to the host from the FPGA instead of bools, the FIFO can be 1/32 as large. And the host side can read from the FIFO 1/32 as fast to prevent overflow.

This example VI uses the rotate with carry and a U8 counter to accomplish this. Note the FIFO is configured with U32 data type.

Requirements

 Software

• LabVIEW FullDevelopment System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• If running in a Real-Time context, you will need the LabVIEW Real-Time Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [FPGA] Main.VI and follow the instructions on the Front Panel

Additional Information or References

This example uses a Single Cycle Timed Loop (SCTL) to acquire from the DIO line at 40MHz Onboard Clock speed. Replace the SCTL with a regular while loop if you don't need or can't acquire that fast. Use also a while loop if your IO are not supported within a SCTL.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[StephenB]

Overview

This example demonstrates how to bit-pack multiple boolean values into one unsigned integer on FPGA

Description

When acquiring a digital waveform in LabVIEW FPGA, the return type is a bool. DMA FIFO transfers from target to host are 32 bit width at the lowest level regardless of how the FIFO is configured (bool, U8, etc). So if you intend to do DMA FIFO transfer of a digital waveform from target to host, if you configure the DMA FIFO to be of type bool, the FIFO is then incredibly inefficient (1/32 efficiency). Additionally, when the bool gets to the host, the host stores bools in memory as a whole byte instead of just a bit (1/8 efficiency).

By packing the digital reads into a U32 on the FPGA level before transferring them up to the host, you avoid the inefficiency of a DMA FIFO configured with the bool data type. You also avoid the inefficiency of storing bools in your host side memory as full bytes.

Finally, because you are sending U32s up to the host from the FPGA instead of bools, the FIFO can be 1/32 as large. And the host side can read from the FIFO 1/32 as fast to prevent overflow.

This example VI uses the rotate with carry and a U8 counter to accomplish this. Note the FIFO is configured with U32 data type.

Requirements

 Software

• LabVIEW FullDevelopment System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• If running in a Real-Time context, you will need the LabVIEW Real-Time Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [FPGA] Main.VI and follow the instructions on the Front Panel

Additional Information or References

This example uses a Single Cycle Timed Loop (SCTL) to acquire from the DIO line at 40MHz Onboard Clock speed. Replace the SCTL with a regular while loop if you don't need or can't acquire that fast. Use also a while loop if your IO are not supported within a SCTL.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[StephenB]

Overview

This example demonstrates how to bit-pack multiple boolean values into one unsigned integer on FPGA

Description

When acquiring a digital waveform in LabVIEW FPGA, the return type is a bool. DMA FIFO transfers from target to host are 32 bit width at the lowest level regardless of how the FIFO is configured (bool, U8, etc). So if you intend to do DMA FIFO transfer of a digital waveform from target to host, if you configure the DMA FIFO to be of type bool, the FIFO is then incredibly inefficient (1/32 efficiency). Additionally, when the bool gets to the host, the host stores bools in memory as a whole byte instead of just a bit (1/8 efficiency).

By packing the digital reads into a U32 on the FPGA level before transferring them up to the host, you avoid the inefficiency of a DMA FIFO configured with the bool data type. You also avoid the inefficiency of storing bools in your host side memory as full bytes.

Finally, because you are sending U32s up to the host from the FPGA instead of bools, the FIFO can be 1/32 as large. And the host side can read from the FIFO 1/32 as fast to prevent overflow.

This example VI uses the rotate with carry and a U8 counter to accomplish this. Note the FIFO is configured with U32 data type.

Requirements

 Software

• LabVIEW FullDevelopment System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• If running in a Real-Time context, you will need the LabVIEW Real-Time Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [FPGA] Main.VI and follow the instructions on the Front Panel

Additional Information or References

This example uses a Single Cycle Timed Loop (SCTL) to acquire from the DIO line at 40MHz Onboard Clock speed. Replace the SCTL with a regular while loop if you don't need or can't acquire that fast. Use also a while loop if your IO are not supported within a SCTL.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[StephenB]

Overview

This example demonstrates how to bit-pack multiple boolean values into one unsigned integer on FPGA

Description

When acquiring a digital waveform in LabVIEW FPGA, the return type is a bool. DMA FIFO transfers from target to host are 32 bit width at the lowest level regardless of how the FIFO is configured (bool, U8, etc). So if you intend to do DMA FIFO transfer of a digital waveform from target to host, if you configure the DMA FIFO to be of type bool, the FIFO is then incredibly inefficient (1/32 efficiency). Additionally, when the bool gets to the host, the host stores bools in memory as a whole byte instead of just a bit (1/8 efficiency).

By packing the digital reads into a U32 on the FPGA level before transferring them up to the host, you avoid the inefficiency of a DMA FIFO configured with the bool data type. You also avoid the inefficiency of storing bools in your host side memory as full bytes.

Finally, because you are sending U32s up to the host from the FPGA instead of bools, the FIFO can be 1/32 as large. And the host side can read from the FIFO 1/32 as fast to prevent overflow.

This example VI uses the rotate with carry and a U8 counter to accomplish this. Note the FIFO is configured with U32 data type.

Requirements

 Software

• LabVIEW FullDevelopment System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• If running in a Real-Time context, you will need the LabVIEW Real-Time Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [FPGA] Main.VI and follow the instructions on the Front Panel

Additional Information or References

This example uses a Single Cycle Timed Loop (SCTL) to acquire from the DIO line at 40MHz Onboard Clock speed. Replace the SCTL with a regular while loop if you don't need or can't acquire that fast. Use also a while loop if your IO are not supported within a SCTL.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[StephenB]

Overview

This example demonstrates how to bit-pack multiple boolean values into one unsigned integer on FPGA

Description

When acquiring a digital waveform in LabVIEW FPGA, the return type is a bool. DMA FIFO transfers from target to host are 32 bit width at the lowest level regardless of how the FIFO is configured (bool, U8, etc). So if you intend to do DMA FIFO transfer of a digital waveform from target to host, if you configure the DMA FIFO to be of type bool, the FIFO is then incredibly inefficient (1/32 efficiency). Additionally, when the bool gets to the host, the host stores bools in memory as a whole byte instead of just a bit (1/8 efficiency).

By packing the digital reads into a U32 on the FPGA level before transferring them up to the host, you avoid the inefficiency of a DMA FIFO configured with the bool data type. You also avoid the inefficiency of storing bools in your host side memory as full bytes.

Finally, because you are sending U32s up to the host from the FPGA instead of bools, the FIFO can be 1/32 as large. And the host side can read from the FIFO 1/32 as fast to prevent overflow.

This example VI uses the rotate with carry and a U8 counter to accomplish this. Note the FIFO is configured with U32 data type.

Requirements

 Software

• LabVIEW FullDevelopment System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)
• If running in a Real-Time context, you will need the LabVIEW Real-Time Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [FPGA] Main.VI and follow the instructions on the Front Panel

Additional Information or References

This example uses a Single Cycle Timed Loop (SCTL) to acquire from the DIO line at 40MHz Onboard Clock speed. Replace the SCTL with a regular while loop if you don't need or can't acquire that fast. Use also a while loop if your IO are not supported within a SCTL.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[StephenB]

Found a problem with the example and updated it to fix the bug. (On the false case it needed to reinit to 1 on the counter, not zero)