This document outlines how to use the National Semiconductor SP1202S01RB Differential Sensor Evaluation Board with a LabVIEW FPGA implementation of the SPI (Serial Peripheral Interface) digital communication protocol. This example controls an ADC by way of SPI.
The National Semiconductor SP1202S01RB Differential Sensor Evaluation Board outputs digitized data data to a SPI serial interface accessed through connector J4 on the board. The SPI signals needed for this example are SCLK, CS, SDATA (MISO). For more information on the SPI bus, see Understanding the SPI Bus with NI LabVIEW .
Figure 1. J4 Connector for SP1202S01RB
Using NI RIO and LabVIEW FPGA with SPI Devices
This example uses a LabVIEW FPGA implementation of the SPI bus to communicate with the evaluation board. There are two LabVIEW elements to this example. The first is a LabVIEW FPGA interface that performs the SPI communication. The second is a LabVIEW host API that interacts with the FPGA from a host PC or real-time processor. We have chosen a CompactRIO system with an NI 9401 module to provide connection to the device. The same example can be used with the NI Embedded Evaluation Toolkit along with your own custom designed PCB C Series Module .
For more information on the LabVIEW FPGA SPI implementation and the host API, refer to Implementing SPI Communication Protocol in LabVIEW FPGA .
Implementing an SPI Example in LabVIEW FPGA
Using the host API created for interacting with the LabVIEW FPGA SPI engine, it is relatively simple to communicate with the SP1202S01RB. With the provided example, most of the configuration is provided and moving the program to a different FPGA target is fairly straight forward.
To run the program, open Example_cRIO_Host.vi from cRIO_NatSemi_Example.lvproj. This is the host interface to the FPGA SPI core interacting with the SP1202S01RB. The program begins by opening a reference to the top-level FPGA VI and waiting for notification from the FPGA that it is ready for data. Once the host VI receives notification, the SPI bus is configured for writing a command to the device. This is done by setting the clock mode to 1 (CPOL = 0, CPHA = 0) and asserting CS 1 which is connected to CSb on the J4 connector. By default, the configuration command will be to read the ADC value. This command is then written to the FPGA VI, which sends the command to the ADC.
Figure 2. Example_cRIO_Host.vi Block Diagram
Once this configuration has been completed, the host VI continuously sends the 16 bits needed for a sample to the device and reads back the data. This data is converted into an integer number and plotted. When the program completes, the FPGA VI is reset and the reference is closed.
Figure 3. Example_cRIO_Host.vi Front Panel
To move the example to another target, create a new LabVIEW FPGA project and copy Example_cRIO_Host.vi, Example_cRIO_Top-Level FPGA.vi, and the two FIFOs from this example project. Once the FPGA is recompiled and the correct connections are made, no further configuration is required.
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Using a LabVIEW FPGA implementation of the SPI communication protocol, we can communicate with many distributed embedded sensors. The SP1202S01RB is one of many embedded evaluation boards from National Semiconductor that use this common bus to return digitized data to a master for processing. With LabVIEW FPGA and RIO hardware, or with LabVIEW desktop and a USB-SPI/I2C, it is easy to communicate to National Semiconductor evaluation PCBs.