Example Code

Generate Digital Clock On DIO Line (Using Sample Rate To Loop Time VI)

Products and Environment

This section reflects the products and operating system used to create the example.

To download NI software, including the products shown below, visit ni.com/downloads.

    Software

  • LabVIEW

    Driver

  • NI RIO

Code and Documents

Attachment

Description

Overview

This example toggels the digital output using the selected clock rate based on the 40 Mhz default FPGA timebase.

 

Introduction

The RIO driver installs scaling VIs for LabVIEW Real-Time and LabVIEW to use with FPGA VIs in order to scale and prepare data for the various FPGA functions. One of those functions is the "Sample Rate to Loop Time" VI which can be used to format a sample rate into ticks, microseconds or milliseconds for use with the loop timer VI. This example demonstrates its use with a PCIe-7852R R-Series card to create a digital clock on DIO0 at the requested frequency.

 

Sample Rate to Loop Time.PNG

Requirements:

LabVIEW FPGA 2009 "or compatible"

LabVIEW 2009 "or compatible"

NI RIO 3.3 "or compatible"

NI R-Series device or simulate FPGA target using LabVIEW FPGA

 

Steps to Implement or Execute Code

1.) You will need to port this example to your hardware, but it should work correctly with any FPGA device sold by National Instruments

2.) Compile the FPGA code for your hardware (run "FPGA.vi")

3.) Select the prefered clock rate (toggel rate) for the digital output line using the "Host.vi"

4.) Run the host vi

 

Additional Information or References

**This document has been updated to meet the current required format for the NI Code Exchange. For more details visit this discussion thread**

Asa Kirby
CompactRIO Product Marketing Manager
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Sail Fast!

Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.