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Power Electronics Development Center
Open Source Reference Design: FPGA-based State Space Real-Time HIL Simulation of 3-Phase Inverter
Update January, 2017: You can find the latest version of the floating point state-space and transfer function solvers in the master power electronics IP and examples library. See the Guide to Power Electronics Control Application Examples and IP Cores for NI GPIC for download instructions, folder locations and more.
Update Mar. 9, 2015: The state-space solver is now available as an example for the graphical floating point toolkit, which greatly simplifies development by eliminating the need to scale the state-space coefficients to appropriate fixed point word lengths. The floating point state-space solver is "universal" in the sense that it can simulate any state-space model (up to 9x9) without needing to recompile the FPGA or normallize/adjust coefficients-- making it more powerful and easier to use. A floating point transfer function solver is also available. Both the floating point state-space and floating point transfer function solvers are available as speed optimized (> 1 MHz) and resource optimized (> 100 kHz) versions. To learn more and download the toolkit and solvers, see whitepaper A and whitepaper B.
Update Jan. 16, 2013: The software installers and code for this RCP and HIL system are being updated. In the mean time, you can find an archived version of the state-space HIL reference design here. This code matches the application note below. The HIL reference design is NOT currently included in the latest versions of the Power Electronics Design Guide Code.
Just getting started? View a new introductory tutorial video on FPGA-based HIL simulation here.
This reference design project demonstrates the power electronics design flow from desktop testbench applications, to co-simulation, rapid control prototyping (RCP) and hardware-in-the-loop (HIL) simulation using the LabVIEW graphical system design toolchain.
In-Depth Tutorials and Code Walk-Throughs
Part 1 Tutorial: Use Testbench Apps to Verify before You Compile
Part 2 Tutorial: Use cosimulation to verify your HIL simulation math and calculate switching losses
Part 3 Tutorial: Execute your control code and HIL simulation in real-time to the verify the control system
LabVIEW Project
Here's a summary of what's in the project:
IP Core Testbench Applications: A variety of testbench applications for the LabVIEW FPGA IP Cores included in the project. Always define the functional requirements for each element of your control algorithm before beginning development. Then create a testbench application that tests and verifies that the IP Core meets your requirements. Whenever changes are made, re-run the testbench to verify the code is working before using in co-simulation or compiling to the FPGA target. (The NI Unit Test Framework tools can facilitate this.)
Verify Fixed Point Matrix Normalization Scaling v18.vi: Shown below. Run this and adjust the Vo and Io scaling so that your state-space system maps to the correct fixed point word lengths for simulation in the FPGA. Once you have selected your scaling with no errors on A, B, or U, then click the Run Sim button to run a simulation using both the floating point and fixed point versions of the state-space model. Verify that the error is sufficiently small at the end of the simulation run. Then click on the "Calculate Output Filter Delay Offset" tab and note the Output Filter Phase Offset (pi) value to use for your LabVIEW FPGA based control system.
Compare Fixed Point vs Multisim - 3 Phase Inverter and Load - Sine-Triangle PWM v16.vi: Next compare the results from your fixed-point state-space model (that will be running in the FPGA of the cRIO-9082 system) against the Multisim results. Make sure the Multisim model and the LabVIEW front panel have the same component values. Also enter the correct Output Filter Phase Offset (pi) value to verify you control system is correctly doing the phase alignment to adjust for the output filter delay at the grid frequency.
Basic Cosimulation - Single Level Inverter with 3 Phase Load Controller - Sine-Triangle PWM v07.vi: This is a basic co-simulation application to verify the control system logic with Multisim. This runs faster because it doesn't have the fixed-point state-space model in it. Use this to design and test new control algorithms on the desktop before compiling them to the FPGA for rapid control prototyping. Note that the same LabVIEW FPGA IP cores are linked in this desktop application and in the LabVIEW FPGA control system in that part of the project. If you change the algorithm in one place it is automatically updated in the other, and may require a recompile. For example, if you edit "IP Cores/FPGA DDS TriangleGen IP.vi" in your cosimulation application, it is automatically updated in the FPGA RCP loop. If you want to run an older version of the LV FPGA application, just like to the bitstream file rather than the VI and you won't be forced to recompile before running. However, your desktop co-simulation algorithms will no longer match the LV FPGA RCP algorithms.
Inverter half bridge conduction and switching loss calculation v11.vi: This is a MathScript RT application that calculates switching and conduction losses for a inverter half-bridge stage (upper and lower switches) using the methodology described in this paper (MCBRYDE, JAMES. Inverter Efficiency Simulation and Measurement for Various Modern Switching Devices. Under the direction of Dr. Subhashish Bhattacharya). It is located under the CompactRIO Real-Time processor part of the project to show you Mathscript code executing in real-time. Be sure to pre-allocate your arrays to avoid memory allocation during execution of the simulation.
3-Phase Inverter RCP and HIL\HIL Inverter - cRIO-9082 - FPGA v08.vi: This is the LabVIEW FPGA application that contains both the control system code and the inverter HIL simulation code. If you want faster compile times, use a dedicated FPGA target for the HIL simulation so you only have to recompile when changing the control system code. This takes about 1.5 hours to compile on my relatively slow laptop. If you do all your development and code verification using the desktop co-simulation environment, you won't have to compile to FPGA very often.
Inverter HIL Simulation x86 v04.vi: Shown below. This is the LabVIEW Real-Time application for rapid control prototyping and HIL. Use this to verify the correct behavior of the FPGA based control system executing against a real-time simulation of the inverter. This creates and environment for comprehensive design validation of your control system performance. For example, you can adjust control system tuning behavior and test the robustness of the control system to disturbances in grid frequency/phase/amplitude. Tools like NI Veristand and NI Teststand enable you to develop automated test suites. Any time you change or update your control algorithms, you can rigorously verify the correct behavior of the closed loop control system using test vectors capable of finding the "needle in the haystack" type bug that only occurs under a complex set of test conditions.
Parts List
A hardware bundle is now available with most of the parts needed to replicate this HIL system. Follow the link below for more information.
NI Power Electronics RCP and HIL System
To replicate this reference design, order the following parts.
| Quantity |
Part Number: Description |
Purpose/Description |
|---|---|---|
| 1 | 781787-02: CRIO-9082 RT, 1.33 GHz Dual-Core Controller and LX150 FPGA with Real-Time | High performance CompactRIO with 180 DSP multiplier cores (minimum of 93 required). If your main goal is HIL simulation rather than RCP, the
PXIe FlexRIO PXIe-7966R is recommended. |
| 1 | 779351-01: NI 9401 8 Ch, 5 V/TTL High-Speed Bidirectional Digital I/O Module | Slot 1: High speed digital I/O module used to monitor or externally control the PWM gate drive signals for the six IGBT switches. If used for monitoring only, this is optional. |
| 1 | 781922-01: NI 9924, Front-mount 25-pin D-SUB to screw terminals accessory | Screw terminal accessory for NI 9401 module. Alternately, you could also use a 25-pin DSUB cable (192568-01: 25-pin DSUB, shielded female to male, 1m). |
| 4 |
779012-01: NI 9263, 4-Channel, 100 kS/s, 16-bit, ±10 V, Analog Output Module |
Slots 5-8: Used to monitor the AB load voltage and line-to-line filter and load currents. Note that the currents are not the phase currents in conventional line-to-nuetral format. This is optional. |
| 4 | 190656-01: Cable, 10 Pos Combicon to Pigtail, 1 Meter | DSUB cable used to wire analog output signals from the NI 9263 modules to the control system under test, such as the NI Single-Board RIO General Purpose Inverter Controller (NI 9683) |
| 1 | 782590-01: Eval Kit, NI sbRIO General Purpose Inverter Controller (GPIC) | Deployment-ready commercial embedded system designed to meet the cost, I/O, and performance needs of most high-volume commercial power electronics control applications, including DC-to-AC, AC-to-DC, DC-to-DC, and AC-to-AC converters for smart-grid flexible AC transmission systems (FACTS), renewable energy generation, energy storage, and variable speed drive applications. (http://www.ni.com/gpic) |
| 1 | Design Files: NI GPIC Screw Terminal Breakout Mating PCB Board Template with SKiiP 3 Connector | Interface board for the NI sbRIO GPIC that includes screw terminal connectors for all 134 I/O channels on the NI sbRIO GPIC. Order from your PCB fabrication house of choice. Alternately you can order from Sunstone Circuits using quote number FQR287178 (use at your own risk- this is example PCB only.) Connect the NI GPIC analog inputs to the multicore CompactRIO analog outputs (slots 5-8). Connect 8 channels of the NI GPIC LVTTL digital outputs to the multicore CompactRIO digital inputs (slot 1). |
Below is a photo of the NI Single-Board RIO HIL setup in the table above. (However, a different version of the mating PCB is used.) As you can see, all 16 analog inputs on the NI sbRIO GPIC are connected to analog outputs of the Multicore CompactRIO HIL system. The HIL voltage outputs are scaled to match the signal scaling of the LEM current and voltage sensors of the physical inverter, so the sbRIO GPIC system "thinks" it's connected to a physical inverter. Here is a template for the inverter control code that runs on the sbRIO GPIC (tutorial and download). The gate command signals are sent both to that half-bridge digital outputs and LVTTL digital lines that are connected to the NI 9401 module in the Multicore CompactRIO HIL system.
Note: Optionally you can add two NI 9239 modules to your Multicore CompactRIO HIL system and use them for electrical power measurements (harmonics, flicker, THD, etc.) on both HIL simulated and physical inverter testing systems.
Development Suggestions and Advice
A number of people have asked about what hardware is recommended for real-time simulation of power electronics (inverters, motors, generators, rectifiers, etc.). Here is some information on that, and some other recommendations and tips.
- Although this reference design is based on Multicore CompactRIO, which is an ideal platform for inverter rapid control prototyping (RCP), the best HW set up for HIL simulation is a PXIe chassis with one or more PXIe FlexRIO PXIe-7966R (http://sine.ni.com/nips/cds/view/p/lang/en/nid/210272). You can easily re-compile this application for FlexRIO- just add the FlexRIO to the project and copy and paste all the FPGA items.
- NI has collaborated with partner KGC to develop a special FlexRIO FAM for power electronics HIL. This is the recommended front end I/O for FlexRIO: https://decibel.ni.com/content/docs/DOC-19394
- The PXI Express peer-to-peer streaming capabilities of FlexRIO enable system expandability. Many developers start with 2 FlexRIO units- one is used for HIL, the other is used for RCP. This enables faster compile times- since the control code is typically recompiled more frequently than the simulation code. Sometimes the same system is also used for instrumenting a physical test setup for model validation. Learn more about peer-to-peer strreaming: http://zone.ni.com/devzone/cda/tut/p/id/10801
- Comparison between Multicore CompactRIO and PXIe FlexRIO: The Multicore CompactRIO Spartan-6 LX150 has 180 DSP48A1 multiplier cores. The FPGA works for small to medium size state-space models. To implement both control and HIL for the three phase inverter (9x9 state-space matrix + 3-phase PLL and basic sine/triangle PWM), this reference design uses 93 out of 180 of the DSP48A1 multiplier cores on the Multicore CompactRIO. For higher end modeling, such as the JMAG motor models, you need a FlexRIO; the Virtex-5 SX95T has 640 DSP48E cores.
- NI has a collaboration with JSOL regarding the FEA tool JMAG-RT to develop ultra high fidelity HIL simulation of motor/generators on FlexRIO. This enables extremely fast, high fidelity simulation of the electromagnetics-- this fidelity level is critical for increasing energy efficiency, optimizing control algorithms, etc.. See a comparison of low fidelity versus high fidelity simulation results- note that the torque/current waveforms are quite different. If you design/tune your controllers based on the oversimplified models, you can expect to get a different result when controlling the real thing. High fidelity models are recommended if you require advanced or precise control or care about thermals, harmonics, energy efficiency: https://decibel.ni.com/content/message/28617#28617
- NI has a collaboration with SET GmBH to develop HIL power simulators. These are high speed, high accuracy "emulator inverters" that simulate the power load/system (four quadrant) that the inverter is connected too. Think of it like an electronic/digital dynamometer for simulating the power system (presently up to 200 kW) that the inverter-under-test is connected to. Actually, there are many things you can test with the system that can't be simulated with a dyno (due to bandwidth limitations of a physical dyno). For example, in electric vehicle design the only alternative would be to drive around in the car to tune the control system, absent this kind of high performance power emulator. The simulation models run on FlexRIO with a fiber connection to the power emulator. More info: http://www.smart-e-tech.de/fileadmin/redakteur/bilder/produkte/Motoremulation/FA N310/Motoremulation...
- FPGA based simulation is complex but the NI graphical programming tools help a lot. The ability to test/debug/validate your LabVIEW FPGA code on the desktop is a tremendous help. You can confirm that all the math works correctly by comparing your fixed-point FPGA simulation results to the floating point "gold standard" simulation results (which can be from any simulation tool), before you compile the code to FPGA. As a best practice, whenever developing a LabVIEW FPGA application, you should never click compile before you have tested your code on the desktop. We are beginning to document best practices and recommendations for FPGA-based HIL simulation. The state-space approach works well because it keeps all the equations in first order form, which is critical as the simulation timestep becomes small. There is a new tutorial presentation here: FPGA-based Real-Time Simulation of Power Electronics: Challenges & Solutions
Screenshots
LabVIEW Project:
IP Core Testbench Applications:
Test Pulse Width Modulation, Use in SCTL (Windows).vi
Test PI Fixed-Point, Use in SCTL (Windows).vi
Block diagram of PI control algorithm that executes in a single clock tick of the FPGA:
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Test Frequency Response PID+Notch+LPF (Windows) v05.vi
Verify Fixed Point Matrix Normalization Scaling v18.vi:
Compare Fixed Point vs Multisim - 3 Phase Inverter and Load - Sine-Triangle PWM v16.vi:
Basic Cosimulation - Single Level Inverter with 3 Phase Load Controller - Sine-Triangle PWM v07.vi:
Inverter half bridge conduction and switching loss calculation v11.vi:
3-Phase Inverter RCP and HIL\HIL Inverter - cRIO-9082 - FPGA v08.vi:
Inverter HIL Simulation x86 v04.vi:
SOFTWARE DOWNLOAD
The software installers and code for this RCP and HIL system are available for download as part of the power electronics design guide.
Hi Sammak,
Most likely you don't have the NI Multisim Co-Simulation Interface installed. This is an option when you install Multisim- be sure to install NI LabVIEW 2011 SP1 and the NI Control Design & Simulation Module first, and then install the NI Multisim Full, PowerPro or the NI Multisim Education Edition. See this tutorial for screenshots of the installers, where you can see the option to install Co-Simulation.
Note: Co-Simulation is not supported with NI Multisim Base.
The software installer download links are here.
I'd recommend you move to the new graphical floating point version of the FPGA state-space simulator. In floating point, it's a "universal simulator" meaning you can simulate any state-space model without needing to (change the data types and) recompile the FPGA. Also, it includes loops used to write the A and B matrix coefficients in run-time. In the old fixed point solver, I believe you had to load them into FPGA RAM initialization values before the compile. The loops to write the A and B matrices (one column at a time) are on the right side of the screenshot below.
Here's the contents of the FPGA subVI that loads the matrix coefficients during run time. Since the state-space solver is a multi-channel implementation, the coefficients for N number of state-space models can be saved in FPGA RAM. A Column Address below refers to which Model # should be written. The Model # input to the solver (see above) determines which of the N models is simulated (taking inputs and calculating new outputs for a single timestep) at any given time.
For an example of calculating the matrix coefficients and loading a set (N number) of state-space model into the FPGA, see "../HIL Simulation\State-Space Solver\subVIs\[RT] cRIO-90xx Global Optimization Function.vi". Note that Mathscript Real-Time code is used to calculate the matrix coefficients based on the parameter values for capacitance, inductances and resistance. This particular state-space model (for an inverter 3-phase line reactor filter and reactive load) is detailed in this paper: SINE-DELTA PWM INVERTER, JIN-WOO JUNG, PH.D STUDENT
http://www2.ece.ohio-state.edu/ems/PowerConverter/Sine_PWM_Inverter.pdf
Note that the optimization example (part of which is shown above) is set up to identify the state-space model parameters based on measured time-domain and/or frequency domain (Bode plot) data. Alternately, you can use it to identify circuit parameters that match your design goal criteria.
Let us know if you have any follow up questions.
Best Regards,
BMAC
