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FPGA Help

Hello Everyone

I am graduate student in the Chemistry department at UWM.  I am running out of avenues here for this project I am working on.  I have been working on this FPGA project for several months now and have come up against a wall here.  I spoke with several engineers over the course of six weeks and made virtually no progress on my project.   I was wondering if there was anyone in the area here that would be able to help? 

Thanks

Ryan

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Ryan, what is the challenge?

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The hardware that we have is PXI 1071 chasis, 8108 controller, 7965R FPGA, and a 5761 digitizer. 

This is the VI I am stuck on.  The I/0 module in the top loop is the laser photodiode that I am trying to monitor.  I am trying to collect the data for a until after the peak is collected.  the middle loop is sending the data from the FPGA VI to the host vi.  The bottom loop is the loop that triggers the laser to fire by using the PFI connector. 

This is just one portion of my larger project.  In testing this VI I and triggering the data collection and laser triggering off the OK button, in the future it will be triggered off another signal. 

I am having an issue with the aser triggering.  When I do that in its own VI I can delay the laser trigger up to 10 seconds.  However when I try to do this in this VI the laser doesnt trigger after times longer than 15 milliseconds.  If it does, the peak does not appear in my data collection.  When I trigger the laser and the peak does show up, the timestamp for the peak does not change. 

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Hi rschmeling,

I'm not much of an FPGA expert but I would recomend posting you quesiton on th FPGA fourms found @

http://forums.ni.com/t5/forums/searchpage/tab/message?submitted=true&type=message&q=fpga&page_size=5...

If that doesn't work you can try an contacting an NI Application engineer from this page.

http://sine.ni.com/psp/app/doc/p/id/psp-434/lang/en

Mark

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Ryan,

Have a look at the attached file (LV2013, let me know if you need it in an earlier version).   It may have been the way the program opened on my computer, being that I do not have the entire project, but there is certainly the possibility for a race condition.  Check my note next to the lower loop to see if that is the functionality you are looking for.  If that is the case, this loop will keep the order of execution in a way that the important data is captured.

Josh

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Hey Josh

Thanks for looking at it for me, would you mind sending it as 2012 version?  I dont have 2013.

Thanks!

Ryan

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