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How to build a 2D LUT in 9606 FPGA target

Hey guys, I am working on a motor control program, and I need to build a 2D LUT in FPGA target of 9606. But memory blocks in FPGA only support 1D LUT. So, I tried to creat a 2D array contanst in FPGA, however, this didn't work niether, as shown in attached figure.

So, what am i supposed to do? Any guide or example will be appreciated!

http://i.imgur.com/5A4VsnI.png

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Here is a new example for a 1D look up table with linear interpolation which uses FPGA RAM memory to store the table. This could easily be extended to create a 2D look up table. To do so, use the attached code as a template, add a second FPGA RAM memory table and modify the interpolation math to bilinear interpolation. Or you could simply use two of these 1D interpolation cores and implement the bilinear interpolation math externally.

Here is the block diagram of the FPGA IP core for 1D look up table with linear interpolation. The equations are documented on the block diagram.

FPGA LUT with Interpolation IP Core.png

Here is the block diagram of the Windows VI that initializes the FPGA RAM look up table. In this case, the table is initialized to the following equation, which is based on a curve fit to measured data for magnetic inductance versus position. Note that the ** operator denotes the power law operation ^.

y(x) = 1.3537188923E-02*x**-3.8060195915E-01 = 1.3537188923E-02*x^-3.8060195915E-01

Init LUT.png

To re-initialize the FPGA RAM Memory table, go to the [FPGA] y(x) LUT.vi IP core block diagram, right-click on Memory and Configure. On the General tab, check that Requested number of elements = Size in the initialization VI, confirm that the Data Type matches the initialization VI, and then navigate to the Initial Values tab. Set the VI Path to point to the initialization VI, ..\IP Cores\IP Cores - LabVIEW FPGA\Look Up Tables\Initialization\Init y(x) Look Up Table.vi. Then click Run VI and OK.

Initializing the FPGA RAM LUT Memory.png

Note: To reduce resources, I recommend replacing the floating point math operators in the IP Core with shared non-reentrant functions from the floating point toolkit. See this GPIC magnetic levitation control and FPGA real-time simulation project for examples (download).

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Thank you very much for your example, it helps a lot. I know that one can use two 1D memory blocks to create a n(row)*2(column) LUT. However, if I want to create a 40*40 dimension 2D LUT, it means that 40 1D blocks are needed. It's a disaster when the dimension of 2D LUT is larger! 

So, what am I supposed to do? 

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Maybe a somewhat lower level solution would be better. You could save your data in the block ram and access them by constructing the address bitwise. Let us assume that your 2D array is 64x64. You can construct the address from 2x6 bits. First 6 bits address the line and the other 6 the column. The interpolation math remains the same as before, and the total memory requirement is 32x64x64 bits (32bit for Single). Hence the memory block will use less than 9 ram blocks in the FPGA (out of 116 in the Spartan 6LX45).

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Seems like the best way is what you said. Thank you.

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