05-06-2015 06:23 PM
I am getting this VISA error when opening either of the RS232 ports on the Dev Board and am using the DevCLIP.
It's not clear from the documentation which is 'native' RT serial port on the DevBoard - but I get this error when attempting to open COM1 or COM2.
It's pretty clear that Serial1 is COM1, the 'dedicated console' out (I recall using this as a serial port on cRIO - should it also work on the SOM?)
I might be missing the bitfile for the FPGA component of the Serial?, but don't see from the documentation where or exactly how to deploy the serial bitfile or if one is needed?
Regards
Jack Hamilton
Here is the installed software for the 9651 with the VISA component.
05-06-2015 07:14 PM
Hi Jack,
My assumption is that the cause will likely be different for COM1 and COM2. To give some background, COM1 does not require a bitfile loaded to flash because it is always present, so it can be enabled as console out. COM2, however, does require a bitfile loaded to flash as it consumes DIO lines. When COM2 is enabled in the CLIP Generator, it enables the proper routing and instantiates the UART in the FPGA fabric. At this point, the CLIP Generator has just generated code, which is why the code must first be compiled and downloaded to flash, so it is set up on the target.
COM1
For COM1, I would verify that the 'Enable Console Out' startup setting is disabled. If the console is enabled, it will hinder your ability to use it as a VISA port.
COM2
As mentioned, you'll need to have a bitfile downloaded to flash to support COM2. Make sure you have the Dev Kit CLIP loaded into the LabVIEW project. Then, compile a blank VI, and download it to flash.
05-06-2015 09:35 PM
Got it working. Had to set the VISA resource to "ASRL1::INSTR" which worked over "COM1". At this point I have no FPGA serial bitfile included. And I did not have to add any more installed software.
So it appears the Serial1 is native to the RT side.
05-07-2015 09:52 AM
Just to clarify, Serial 1 is like all other serial ports on the sbRIO-9651. The UART itself is in the FPGA. It is just always included in your FPGA compiles. It is also in the default bitfile. This bitfile is loaded when no user bitfile is present.
05-07-2015 10:21 AM
Nathan_R,
Thanks for the clarification.
Regards
Jack Hamilton
05-07-2015 12:55 PM
Also, to add to the conversation, I posted training on this community a while back that may help out if you run into questions between what the interface is named, the serial type, and the corresponding MAX name.
It is on slide 23 of this training. I hope this helps!
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