Brainstorming: CompactRIO Simulation Requirements

[Caseyw]

LabVIEW Real-Time Developers: what if you were able to simulate a CompactRIO or other RIO target during the development process? Please comment on what your absolute minimum requirements would be. Would these include:

- Communicating via shared variables or other network communication methods in simulation?

- Communicating between a simulated LabVIEW Real-Time application and simulated FPGA via DMA FIFO or host interface?

- Programmatically generating data to feed into scan mode I/O, or generating random values for scan mode I/O?

- Executing compiled .out libraries in simulation?

Thank you in advance for your feedback; any other insight on how you would take advantage of simulation would also be helpful.

Best Regards,

Casey Weltzin

Product Manager, LabVIEW Real-Time

National Instruments

casey.weltzin@ni.com

[Brian_K.]

Our current RIO IO simulation mechanism (through a Simulated I/O VI) has no concept of state.  In otherwords if I wanted to send a waveform through an IO channel, I have to make a very cludgey solution (though asynchronous VIs and such).  Considering a lot of people want to simulate particular signals into the cRIO IO this make the feature very difficult to use.

[ryank]

This is a really annoying sticking point right now (specifically the DMA bit):

- Communicating between a simulated LabVIEW Real-Time application and simulated FPGA via DMA FIFO or host interface?

The Windows folks can do this with their FPGAs, but RT cannot, it makes creating any sort of automated test system for cRIO very difficult (beyond just testing the system as a whole).

[JimMacD]

In addition to what you have listed:

Minimum:

-CPU/memory usage – effect on system hardware

-Ability to select different cRIO model #s to see what minimum system requirements need to be (i.e. will a lower model cRIO have enough power to execute tasks)

-Include IO Servers (i.e. MODBUS I/O Server) and simulate connection/values

Additional Features:

- Allow the use of the RT Trace Toolkit on simulation

-IO Aliases connected to simulated hardware (easier to move to physical target then)

This would be a really helpful tool. One thing that I have had an issue with in LV 2010 is changing the name of my cRIO target from my development target to the actual target. Some of my shared variables do not correct the binding referance to reflect the new name, even after modifying the alias text file. Perhaps this is something to work out for the simulator?

[James_McN]

I think any form of RT simulation to allow development without a device present would be useful.  Or at least enough to allow FPGA simulation without the RT present as this can be a real pain at times.

[Caseyw]

Hi All,

Thank you to those who have already posted some feedback; keep the replies coming! In the interest of gathering the most productive data, please be sure to separate out your minimum requirements from those things that would be "nice to have".

I would also like to specifically ask for comments on the necessity of simulating compiled .out libraries; is this a minimum requirement for you?

Best Regards,

Casey Weltzin

Product Manager, LabVIEW Real-Time

National Instruments

casey.weltzin@ni.com