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Overview
The example demonstrates how to program two PWM signals with a adjustable delay between both signals.
Description
Generating multiple pulse trains using LabVIEW FPGA is relatively simple to code. In this example ('PWM with Offset.vi') two PWM signals are generated with an adjustable delay between both signals (phase shift). There are two implementations doing the same task but the 'Single Cycle Timed Loop (SCTL)' implementation is a little bit more efficient than the 'While Loop' implementation, but more low-level and a little bit harder to read.
Also there is a second example ('PWM with Offset (no FPGA).vi') that only uses standard Windows LabVIEW functions that do not need the LabVIEW FPGA Module. Please be advised that this example is only for demonstration purposes and will very likely not run on a Windows system with full determinism.
Requirements
Software
Hardware
Steps to Implement or Execute Code
Additional Information or References
FPGA implementation
Implementation without FPGA
KnowledgeBase: Simulate FPGA Hardware Targets Using the Project Explorer with LabVIEW
Tutorial: Testing and Debugging LabVIEW FPGA Code
**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text 'NIVerified'. Read here for more information about the new Example Guidelines and Community Platform.**
Description-Separate-2
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.
When converting this code to FPGA, the original code gave errors as the DBL type was not supported for FPGA. I've updated the code and converted all DBL to Fixed Point data type. (9/14/2011)