Overview
This project instantiates two individual Aurora 8b10b x4 cores on a PXIe-6591R @ 3.2Gbps. The LVFPGA diagram can generate and check patterns. This is intended as a starting point for customers needing to communicate to another Aurora 8b10b device. Each Aurora core is connected to an SFP+ port on the PXIe-6591R, and is capable of transmitting and receiving simultaneously.
Description
The Xilinx .xci file is included in the zip file for the user to see the core settings or modify them:
Hardware and Software Requirements
NI PXIe Controller
NI PXIe Chassis
PXIe-6591R
SFP+ Cable
LabVIEW 2016
LabVIEW FPGA 2016
Instrument Design Libraries for High Speed Serial Instruments 16.1
LabVIEW 2016 FPGA Module Xilinx Tools Vivado 2015.4
Steps to Implement or Execute Code
Download the zip file, navigate to the documentation folder, and open Aurora Pattern Controller.htm for instructions on how to run.
Additional Information or References
Download the zip file, navigate to the documentation folder for more details.
