Adding CLIP with MMCM results in IDELAYCTRL Error

[tduffy]

Could someone assist me in understanding the NI recommended flow for adding an MMCM to a CLIP for the NI-9051?  I have created a an XCI file within Vivado 203.4 and then generated the output products ( which creates a DCP ).  I then instantiate the DCP file within some VHDL code, and then instantiate that VHDL code in the CLIP file.  I have incremented the number of required MMCM's in the CLIP XML from 0 to 1.

I receive the following error output:

LabVIEW FPGA:  The compilation failed due to a Xilinx error.
Details:
ERROR: [Place 30-519] REFCLK pin of IDELAYCTRL instance 'IDELAYCTRL_INST' is driven by 'PLLE2_ADV_IDLY_inst'{PLLE2_ADV}. This will lead to unroutable situation. The REFCLK pin of a IDELAYCTRL instance should always be driven by clock buffer
Phase 1.1.5 Implementation Feasibility check | Checksum: 12d07cc50
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1209.328 ; gain = 0.000
Phase 1.1 Placer Initialization Core | Checksum: 12d07cc50
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1209.328 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 12d07cc50
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1209.328 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 12d07cc50
Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 1209.328 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
10 Infos, 0 Warnings, 2 Critical Warnings and 2 Errors encountered.
place_design failed
::ERROR: [Common 17-69] Command failed: Placer could not place all instances
    while executing
"place_design -directive "Default""
    (file "C:/NIFPGA/jobs/Mg9LiN0_WUKFGq0/place.tcl" line 5)
    invoked from within
"source "C:/NIFPGA/jobs/Mg9LiN0_WUKFGq0/place.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Mon Jun 29 11:43:33 2015...
Compilation Time
---------------------------
Date submitted: 6/29/2015 11:40 AM
Date results were retrieved: 6/29/2015 11:43 AM
Time waiting in queue: 00:06
Time compiling: 03:04
- Generate Xilinx IP: 00:01
- Synthesize - Vivado: 02:26
- Optimize Logic: 00:21
- Place: 00:05

I suspect this is due to conflicts in the LabVIEW FPGA boilerplate HDL code, and me instantiating an MMCM.  Any support is greatly appreciated.

Thanks,

-TD

[nturley]

Easy Way: Generate a derived clock in your LV FPGA project and send the clock from the LV FPGA diagram into the CLIP

Medium Way: Use the CLIP Generator increment the number of required MMCMs. Instantiate the MMCM primitive (either a MMCME2_BASE or MMCME2_ADV) in the CLIP VHDL. The "Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide" (UG953) has example code how to do this.

Hard Way: Write a wrapper for your DCP file, and create an edif netlist of that component. I believe Vivado calls it Out-Of-Context modules. Then edit the CLIP VHDL to instantiate your netlist and use the CLIP Generator to increment the number of required MMCM's. You'll also need to edit the CLIP XML to add additional source files.

The first two approaches were pretty easy for me. I had a lot of trouble with the third approach, so I'd only do that as a last resort.

[tduffy]

nturley,

Thank you for your help.  I went with the "Medium Way" and was successful.  My issue was actually related to how I was using the 40 MHz clock coming into the CLIP.  It appears ( and I've only done a little looking into this ), that I can not load the clock that is driving the MMCM within the CLIP.  Vivado doesn't seem to happy about that.  I suspect this is because there is a BUFG ( or similar ) buffer right on the othe side of the CLIP boundry within the NI HDL code.

Thank you again for your assistance.

-TD