it's very near of what i've imagined using High Performance port of Zynq
to DDR direct access for zero latency.
Yeah, we experimented with the HP port. We chose to hook into our existing DMA engine (which hooks to ACP), to make it easier to port our work to non-Zynq architectures and to get cache coherency which buys us a smaller round trip time for control loops.
Any Degraded performance on Linux once this memory is allocated?
That's a difficult question to answer. The CPU doesn't need to do any work for the FPGA to access the memory so the simple answer is no. Whatever you do on HMB shouldn't affect what the RT is doing.
The more complicated answer is there are potentially shared resources between HMB and your application. The biggest one is probably the DMA bandwidth. HMB, FIFOs, and Scan Engine all hook into the same DMA engine so they are all competing for DMA bandwidth. There's also things like DRAM controller bandwidth and cache thrashing which could theoretically affect your performance, but in practice I haven't been able to measure them (probably because it's buried in the noise).
