SOM burnout program? Something like SuperPi/Prime95/3DMark/IntelBurnTest?

[jiangliang]

I did notice NI did quite a lot job on SOM heat performance, but now I have to build my own chassis, I did like what NI recommanded my to do, put the SOM direct contact to the chassis, yet the chassis itself is not very big, and I would like to have a idea about the worst condition heat manage performance.

I have some idea, but not quite sure if it covers all:

1. make RT running at 100% cpu, for both core.

2. at the same time, make memory bandwidth usage at a high level, which make sure memory controller and memory itself are fullly loaded.

3. also make flash running at a high level usage

4. make a near 100% usage code at FPGA, and make it running at a high frequency, like 160Mhz or so.

Am I doing that right? Or maybe someone can tell us how NI did their heatsink performance benchmark? Maybe NI can provide something like SuperPi in PC benchmark?

[Deagle]

Jiangliang,

I think the first question we need to answer is: how customizable will your end application be? Will it have a somewhat fixed FPGA personality and fixed I/O, or is there a wide range of applications that could be run on this product which could have differing thermal performance?

Thanks,

Bryan

[jiangliang]

Customer want us to give a opensourced solution to them, and them intent to make a 2nd round of develope based on my HW intergration, so it hard to tell how much FPGA/ARM resource will be used, in that case I would need the worst case heatsink/speard performance benchmark.

[Deagle]

Jiangliang,

In general, our recommendation for your CPU usage is to "restrict your application to using no more than 80 percent of the available CPU." So I think trying to hit 100% CPU usage is excessive and will likely interfere with important peripheral functions like networking.

On a similar note, I think any end application will be far below the 100% FPGA utilization as well. You'll want to take into account all of the IO being utilized on this device, but regarding the FPGA logic, the closer you can get to what you expect the end application to be, and adding a margin, the better.

Thanks,

Bryan