Dual Channel Continuous Acquisition on the 5640r?

[cdschmit]

Hi,

I'm jumping posts from the Real-Time to the IF-RIO community (you can see  http://forums.ni.com/ni/board/message?board.id=280&message.id=8356&jump=true#M8356 for more background on my problem).

I would like to be able to write synchronously to two channels as well as achieve continuous acquisition on the other two channels.  I realize that I will need to reduce my bandwidth to be able to do this, but that is not a problem.  I was able to get the ni5640r (Single Channel) Analog Input and Output project (NI's template) working for continuous acquisition under the advice of Jerry_L.  But, in trying to apply the same fixes to the ni5640r Dual Analog Input and Ouput project (again, NI's template), the acquisition is not continuous.  I've attached my current version of this project.  I would greatly appreciate it if someone could offer advice on how to move forward with it.

Thanks!

Chris

[cdschmit]

Sorry, here is the attachment.

Chris

[jaced]

Hi Chris,

I looked over your code and could not find anything that looked wrong. I then built my own version and it seemed to work, which then led me to recompile your code and it now works for me. I am not sure what happened on compile on your end but it appears to have caused this. Try to recompile your code and that should fix the issue. I have attached my bit file also, All I have done is modify the dual channel example fpga code in the same mannor you explained in your previous post, so using this bit file with that example should not be an issue. Please let us know if this does not solve your issue. 

[cdschmit]

JaceD,

I think you may be right.  I tried to recompile twice today, and it failed both times.  First, it complained about not finding the compiler (listing the IP address of this same machine on which LabVIEW and the IF-RIO is hosted).  Second, it just failed after churning for an hour...I think this is why (from the xilinx log):

Checking expanded design ...
   'window/theVI/n_0000013E/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIr
   qNum/BlkRdy.iRdyPushToggle_msx' with type 'DFlopBool_1' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   or the misspelling of a type name. Symbol 'DFlopBool_1' is not supported in
   target 'virtex2p'.
   'window/theVI/n_0000013E/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIr
   qNum/BlkOut.oPushToggle0_msx' with type 'DFlopBool_1' could not be resolved.
   A pin name misspelling can cause this, a missing edif or ngc file, or the
   misspelling of a type name. Symbol 'DFlopBool_1' is not supported in target
   'virtex2p'.
   'window/theVI/n_0000013E/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIr
   qAck/BlkRdy.iRdyPushToggle_msx' with type 'DFlopBool_1' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   or the misspelling of a type name. Symbol 'DFlopBool_1' is not supported in
   target 'virtex2p'.
   'window/theVI/n_0000013E/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIr
   qAck/BlkOut.oPushToggle0_msx' with type 'DFlopBool_1' could not be resolved.
   A pin name misspelling can cause this, a missing edif or ngc file, or the
   misspelling of a type name. Symbol 'DFlopBool_1' is not supported in target
   'virtex2p'.

This is all pretty cryptic...I was hoping you might have some insight.  In the meantime, I'll keep trying to find some consistency in the compile errors.

Thanks!

Chris

[jaced]

Hi Chris,

I have been told there was an issue similar to yours that was corrected by following the steps in the following KB:

http://digital.ni.com/public.nsf/allkb/A45687D827A81D6E86257195007807B3?OpenDocument

If this fixes your issue can you please post back so that we can update our documentation. If this does not solve the issue I would suggest a reinstall of LabVIEW FPGA. 

[cdschmit]

JaceD,

On the fifth attempt, the compile completed.  But when I ran the host, I had the same problem discontiguous data.  When I went to place your bit file into my folder (to test it), I realized that there were already two generated bit files there...one that came with the template  ni5640R Dual Chann~96_FPGA Target_ni5640R Dual Chann~A5.lvbitx and a different one that was being generated by the compiler ni5640R Dual Chann~4B_FPGA Target_ni5640R Dual Chann~A5.lvbitx  (Note the 4B instead of the 96).  I used Configure Open FPGA Reference in the host block diagram to point to the generated bit file and it ran without the discontinuities (with sampling rates at or below 3.125 MHz, of course).  I see now how to change the Target Specific Properties... of the FPGA VI so that I overwrite the correct bitfile.  I don't know why the second file was named, but my first problem is therefore solved.

As for the failed compile attempts, I did not find any of the errors mentioned in your post, so I reinstalled FPGA module and FPGA Compile Server and will try to run the compiler again.  I'll post back to let you know if the problems persist.

Thanks for all the help!

Chris