PCI-5640R Trigger Problem and Streaming with FPGA

[wonshil]

I know that the trigger signal is make start generagte or sampling,

And Tow different board or device make sync each other with Ref CLK and Trigger signal.

But two PCI 5640R board don't work like that.

I use same Ref CLK and they are PLL locked , and shoot same ext trigger signal. but all most different work.

If they are fixed offset phase or delay time, I can solve that but each time (when play) offset is changed.

Then How can I play streaming full sample rate with FPGA code?

[ColeTrain]

Hello Wonshil,

I apologize as I think there is a translation issue here that is preventing me from properly understanding your problem.  I understand that there is a skew between runs (ie the delay from when the trigger is received vs when something happens) and this will be a variable time that should never be longer than a clock cycle.  However, I do not know what your last statement is referring to.  Are you trying to build an application that streams data through the output once a trigger is received? Are you trying to syncronize the outputs between both cards with little skew between them? Thanks for your furthur clarification.