FPGA onboard and derived clocks

[VarunSreenivasan]

Hi,

I am using a PCIe 7852R FPGA board to collect data at 200kHz from 5 channels. I was quite confident that my collection frequency was correct, because my program was based on a 40MHz derived clock. I had chosen to use a derived clock because the onboard clock was running at 40.02 MHz (instead of the specified 40MHz for some unknown reason that I ignored).

However, today one of the LabVIEW support team members mentioned to me that the FPGA clock frequency may change during compilation and optimization (due to constraints). He pointed out that if the FPGA cannot run that fast, then it will show an error (as one would expect). He also told that in some cases the onboard clock may run faster, but in this case no error will be displayed. I have not seen any errors in the past (which means that the system had no problem with running that fast), however, I am unsure if during any of my compilations my derived clock might have run faster than 40MHz. Can this happen? This will affect the timing of all my previously acquired data. Unfortunately, I did not save any of my compilation logs . 

Thanks very much in advance.

Regards,

Varun

[Haagen-Dazs · Accepted solution]

Hi VarunSreenivasan,

I think what our support meant to say is that the compilation logs will show you that certain chunks of logic could run at higher speeds. During the compilation process the compiler will determine the fastest clock frequency that can be used for your logic and make sure that the clock frequency configured is less than or equal to this value. If you decided to try to run your code at 200 MHz and the logic could not execute that fast then you would get an error. If you decided to run your logic at 200kHz and it is possible to run faster the compilation logs will then show you the max frequency that will work but the logic still run at 200kHz. The code should not execute faster than the frequency that you specified.

[VarunSreenivasan]

Hi Patrick,

Thank you the information. That certainly is comforting. Will the same be true if my loop timer is based on tick counts?

What is a CLIP? According to the compilation log, my CLIP runs at 33 MHz only. Is this something that I need to be worried about? My code is only used for controlling a few optical devices via a/os, while parallely acquiring and streaming into a host PC.

Thank you again, much appreciated.

Regads,

Varun

[Haagen-Dazs]

Hi Varun,

The loop timer would be used in a general while loop and if it is configured for ticks then the ticks will be based off the top level clock. The number of ticks will be the number of clock cycles that execute every iteration of the loop. The correct way to use the loop timer is to place the loop timer in the first frame of a flat sequence structure and the code for the loop in the second frame. In general this will behave as expected except in the case where your code takes more ticks than the ticks of the loop timer. In this case the loop timer is essentialy not there and the loop will run as fast as your code can run using the top level clock.

Loop Timer:

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpga/loop_timer/

I have linked more information about CLIP below. Take a look at the information and determine if this is something that you have configured. If not then I wouldnt worry about it.

CLIP:
http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgahelp/fpga_using_clip_clock/

[VarunSreenivasan]

Hi Patrick,

Thank you for your reply. I believe my code was fine from your description. I have also not implemented any external clocks. So, I think that should be fine as well.

Thanks a lot for helping out.

Regards,

Varun