New output from loop timer express VI that indicates lateness

[StephenB]

The loop timer express VI is very useful to time a loop to an exact rate, however... if you want to be sure the loop is meeting the rate requested... you also have to put in tic count VIs like this:

Since the loop timer express VI already is calculating how long it needs to wait in order to achieve the desired loop time, I would prefer it if at least output a bool that indicated it failed to achieve the timing required.

It would be best if it output the actual tics it waited in like I16 form so it could go negative (indicating the # of tics it failed to achieve timing by.

[stbe]

afaik, the Loop Timer does have an output of the current FPGA tick count ... so no need to use the dedicated tick count here ?

if you have timing issues with this VI, I would consider some improvements (although this would fit better to the LV forums):

* why using the for loop around the while loop - you can (very simply) achieve the for loop behaviour yourself and won't loose extra FPGA ticks

* using the timeout input of the write fifo so not to exceed your desired loop rate

-Benjamin

[StephenB]

Benjamin, You're mostly right. The code posted was just an example though and certainly could be optimized (like removing the tick count express VI because the loop timer already outputs this). However, since the Loop timer already internally does the subtraction and time comparison internally.. I would prefer if it simply output those values.