VI scripting for FPGA programming

[totolemalino]

I didn't find something related to this, so I hope it's a new idea.

I use frequently VI scripting on LabVIEW, it is very useful for example to generate template VI's.

but this feature doesn't exist under FPGA, I mean some code is specific to this module, and I think it would be great to be able to generate FPGA VI's programmatically. For example in my job we make FPGA programming for Magnet Security. Even if global structure is the same for all magnets, we have to adapt a lot of things depending on type of magnet and instrumentation available. The idea would be to create ourself a kind of Magnet Safety Editor based on VI scripting specific for FPGA in order to allow non-programmers, but Magnet specialists, to generate themselves an adapted security system.

It's just an example, but when we see powerful of VI scripting for LabVIEW, it would give great results if it extends to FPGA, and even Real-Time  module, why not? 

[jt_fuw]

Hello, till now I tried very few things via the VI scripting: creating a VI for FPGA

target, putting EIONode-s in its Block Diagram and connecting them; plus AND

gate as an example of a simple standard LabVIEW object.

My idea is: create the program logic in VHDL and add it to a LabVIEW project

as a CLIP; add C-Modules to the project; then use scripting to connect them -

an EIONode defines a connection between C-Module I/O or CLIP instance

terminal, and a terminal in VI BD.

My goal: when making hundreds connections it is easy to make a mistake

- I want making these connections to be driven by a textual information,

which can be even prepared and verified programmatically.

Some my attempt to create EIONode-s on LAVA Group:

https://lavag.org/topic/23675-eionode-a-problem-when-getting-data-type-of-a-newly-created-one/

(after the reply I received there I abandoned an idea to verify data types

 in LabVIEW program and I am going ahead to try what I can do)

I am using LabVIEW 2018; its VI Scripting can create 1132 dfferent

objects (surely most of them cannot by used in FPGA VI), and till now

I have tried very few of them only.