FPGA Desktop Execution Node - array input for simulations with multiple ticks

[Johannes.Wiesmeier]

FPGA Desktop Execution Node doesn’t allow applying new input value for each simulation tick. e.g. simulation of digital filter would require an array of input samples. In each step/tick a new input sample is processed. The VI under test has internal feedback nodes to store data history. The following example is no solution because simulation initializes feedback nodes every time.

[dfjuggler]

Are you sure this is not possible? If you share some sample code I might be able to help you (or understand what you mean).

[Darren]

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