74HC191 counter timing are wrong.

[goshawk]

The timing for the model of the 74HC191 are incorrect. they do not conform to those given in the data sheets.  RCO should only go low for the low part of the clock period, not the entire clock cycle. (See data sheet from NXP as this is one of the few data sheets that has the timing.) As a result simulations with this component are incorrect.

[rolfk]

You do realize that you are in the LabVIEW forum and not in the Circuit Design Suite forum?

[Stephen_C]

Hi goshawk,

Thank you for bringing this issue to our attention. I am not an expert with the inner workings of such devices, but I intend to report this bug to our R&D department for them to investigate further.

Would it be possible for you to upload your code in which this problem is visible for me to forward to the R&D team?

In the mean time, if you can find a correct spice model for the component you can import it into multisim.

Kind regards,

[goshawk]

Hi

I am now in touch with the support team in the Uk. They have seen the problem and raised it with the R and D team. Whether I ever get a correct model remains to be seen. The problem is the ripple carry out signal is asserted low for the entire clock period. It should only be low for the low part of the clock period.