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12-24-2013 04:05 AM
Hi All,
Merry christmas to all!!
Here is my problem.. I am trying to generate a 3-bit CRC with the polynomial x^3 + x +1. I am trying to do it in FPGA.
I am not allowed to use a loop within a timed structure and cannot use remainder function in FPGA. Hence can any one tell me how can I go with this??
Thanks,
Yogesh
12-24-2013 05:38 AM
How many bits are in the message you are trying to perform a CRC on? Instead of using a loop, you could serialize the CRC process, but that could be a lot of calls to the same code.
12-25-2013 10:00 PM
Hi,
I need to perform CRC on a total of 26bits. So, doing it serially is not a good option.
Thanks and regards,
Yogesh
01-02-2014 09:44 AM
Can you give more insight into what performance metrics you need? What is the throughput of the system? What latency can be accmodated?
Depending on those factors, you might not even need the SCL and can instead just use a regular while loop (at least for most of the code).
01-02-2014 11:23 PM
Hi Dragis,
I have the STL in the main FPGA VI. This is used as a SPI driver. I cannot replace this with a while loop.
Thanks,
Yogesh
01-03-2014 09:33 AM
Thanks for the information. In that case you can use the High Throughput Math Library nodes to perform the calculation. Those nodes perform the same functions as the primitives but they are pipelined (configurable) and have handshaking signals to deal with synchronization. Different factorizations of your polynomial can help with reducing the latency of the operation.