Changing the SNTP period programmatically

[DeOdderKeith]

In following the example for setting the SNTP period the ni-rt.ini file must be updated, and the cRIO re-booted. Can I update the INI file while the cRIO is running, and re-Boot the cRIO when I need to change the update period ?

There is a concern about the cRIO clock "drift" over time.

Additionally, does anyone have any statistics on this "drift"?

DOK

[Robbob]

Dok,

The .ini file can indeed be changed while the cRIO is on, and when you reboot the controller, it will read the file and apply those settings. You can simply FTP into the controller and modify the file, this is the easiest way.

As fas as clock drift, the manual specs out Accuracy to be 200 ppm; 35 ppm at 25 °C, but this is more of a drift over temperature range rather than drift over time.  I am not sure on that, sorry.

[DeOdderKeith]

Thanks for the info.

I've followed the steps, and had to Re-Boot the cRIO, but also had to re-load the software (via MAX).

My question is in 2-parts:

1. If I were to try to implement this in the field if would be impractical to have to re-load the software through MAX every time I try to update the SNTP Period.

As an option,

2. is there a way to retrieve the SNTP vi a piece of application software ? this way I can update the period through my application, rather than allowing the cRIO to do this automatically

[DiscoBall]

DOK,

Why did you have to reinstall the software? Are you following the steps listed in KnowledgeBase 493C8ELX: Configuring CompactRIO Real-Time Controllers to Synchronize to SNTP Servers? Perhaps NI Developer Zone Tutorial Reference Example for Setting cRIO VxWorks System Time may be helpful?

[acanivell]

Hi Robbob

A little bit off the topic question ...

I am using CRIO 9073 for accurate frequency measurement.

I am not sure what they mean when they specify 200ppm of accuracy in the CRIO manual:

a) Is it that for a clock of X hertz that you place in your VI you will have an error of X*200/(1,000,000) [Hz]

b) Or is it that for a clock of X hertz that you place in your VI you will have an error of [Internal-clock]*200/(1,000,000) [Hz]. Where internal clock is the maximum clock of the system.

Hope I made my self be understood...

[DiscoBall]

Hi acanivell,

 
The specification listed in the manual applies to the hardware clock internal to the cRIO that the System Clock dirivies its time from.

You say you are trying to measure frequency, and that usually depends on the module that you are doing the measurement on. What module are you measuring frequency with?

[acanivell]

Hi DiscoBall

"The specification listed in the manual applies to the hardware clock internal to the cRIO that the System Clock dirivies its time from."

Then I can not find the clock rate in the CRIO 9073 manual or datasheet, only the processor speed.

In any case, I was thinking to use 9402 for acquiring the signal (1Khz to 100Khz range) and then use the LV FPGA to program a counter in the FPGA that can do the trick.

Actually I would love to use something like the PXI 6608 counter but in CRIO platform.

[DiscoBall]

Hi Acanivell,
 
The clock rate of the cRIO 9073 is listed at 266 MHz (found on the product page, not the manual). The Real-Time System Clock derives its clock from that clock and no other inaccuracies are added.

However, the FPGA does not use the Real-Time Internal Clock, but its own clock base of 40 MHz and measuring a pulse of a signal module would follow the basic steps of looking for a transition, start a counter, look for the next transition and once found grab that tick count. The difference between the two counts is your high or low pulse (you can modify the transitioning to find frequency). Each tick of the FPGA is 25 nanoseconds. I am unsure about the accuracy of the 40 MHz clock on the FPGA.

I noticed that you have other posts on this topic and will try to respond to those too.

[acanivell]

Hi Discoball

Yes, I have been asking about this frequency measurement issue  in a lot of places that are somehow related.

I also started my own thread http://forums.ni.com/ni/board/message?board.id=40&message.id=7560#M7560 but nobody replied.

I made some numbers on derived clock stability that I added in that first thread.

I even checked the XILINX spartan 3 manual, but did not clearly find anything on the stability of the clock. I can not evaluate the performance of the CRIO FPGA for frequency measurement without this information.

So then info in the manuals is that the FPGA runs an oscillator with 200ppm (or 35ppm at 25C). According to you it is 40Mhz, but this value, I do not need as stability propagates to derived clocks proportionally. So any clock I generate will have this 200ppm or 35ppm stability. This should be enough for my calculations though.

Thanks!

Message Edited by acanivell on 07-30-2009 03:46 AM

[glk]

You must be aware of that there is a bug in the firmware regarding sntp. The cRIO controllers only synchronize once after reboot!! There are no continous synchronization.