[FPGA] Analog I/O minimum number of clock cycles

[gerardpc]

I'm lately trying to optimize my LabVIEW FPGA code by reducing the minimum number of cycles that each while loops needs. The card I'm using is a RIO 7852R (40 MHz clock), and right now my bottleneck is the Analog I/O function, which apparently I cannot run inside a while loop faster than 100 cycles. 

Is there any way to improve it? According to the specs it should be able run at 1 MHz, so around 40 cycles per loop.

[Duffy2007]

Hello gerardpc,

can you provide a screenshot, how the benchmark was done or the FPGA code?

Is the analog in and out in the same loop?

This link could be helpful:

Optimizing your LabVIEW FPGA VIs: Parallel Execution and Pipelining

[gerardpc · Accepted solution]

I found the problem. I was accessing the same Analog input from two different loops. This reduced the speed about two times.

After modifying my code with a FIFO instead of a dual direct access to my input I could reduce the number of clock cycles to about 50 (close to the theoretical optimum of 40).