Hello,
I am writing a program whereby I simultaneously need to stream data to and from the FPGA target. I would imagine this is a rather common producer/consumer scenario.
The host continuously streams output data to the target via a Host to Target DMA FIFO and the target subsequently outputs this data. At the same time, the target makes some measurements and streams this data to a Target to Host DMA FIFO for the host to download and save. This seems roughly to work, except for some FIFO buffer underruns/overfills that I am trying to debug at the moment.
I would like this process to run as fast as the hardware can. My question is what kind of loops should I use to achieve maximum throughput/speed. Should I use normal loops and sleep on the DMA FIFO read/writes (by wiring -1 to the timeouts)? Or else, should I use timed loops wiring 0 to the timeouts and make my timeouts by hand, e.g. by counting a maximum number of ticks that happened to timeout before declaring a buffer underrun/overfill?
I guess another way of asking this question is how can I achieve maximum throughput/speed with DMA FIFOs? Is this achieved by using timed loops? Else, if using a normal loop, is this code going to be compiled such that a large chunk of data is going to be transferred fast between the Host and Target?
Thank you.
Jacob
