LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

FPGA_For loop inside timed loop error

Dear all

I need to transmit an array contain three elements, so I should use For_loop for FPGA_FIFO, knowing that I used timed loop when I build FPGA code an error shown that "You cannot include this function in a For Loop when the For Loop is inside a single-cycle Timed Loop."

any help!!

FPGA screenshot

Untitled.jpg

 

 

 

 

0 Kudos
Message 1 of 8
(2,961 Views)

Hi jafar,

 

easy fix: don't use a SCTL (single cycle timed loop)!

Use a standard while loop with a delay function inside…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
0 Kudos
Message 2 of 8
(2,943 Views)

They simply aren't supported as every loop in LabVIEW FPGA requires mutliple cycles to complete (except the single-cycle loop!).

 

For many things you might just manually duplicate the code but in your case you won't be able to as you won't be able to write multiple times to a DMA FIFO in an SCTL.

 

You have two options:

 

1. Remove the SCTL as GerdW suggests.

2. Create a new intermediate FIFO which takes all 3 elements as a cluster or similar. This writes to a standard loop which can send them sequential up the DMA FIFO in a seperate loop. This is how I have handled this case in the past if you need the SCTL (I suspect you might by the code comments)

James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
Message 3 of 8
(2,931 Views)

thank you GerdW for your reply

but in this code, timed loop is required, otherwise the code will not work correctly!!

0 Kudos
Message 4 of 8
(2,926 Views)

Thank you James_McN for your reply

can you help me how to represent 3 elements as a cluster then transmit data to FIFO?
because I tried that and an error appear that wires have different types.

0 Kudos
Message 5 of 8
(2,915 Views)

This must be a Target Scoped FIFO, please confirm that.

Create a typedef which is a fixed size 1D array of U32.  Edit or make a new Target Scoped FIFO and in the datatype it will have an option for Custom Control (last one I think).  Select that and then browse to this new typedef.


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
Message 6 of 8
(2,898 Views)

Thank you Terry_ALE for your reply

a Target Scoped FIFO needs For_loop, which its use not allowed in timing loop! 

0 Kudos
Message 7 of 8
(2,869 Views)

That is not true. Please follow my instructions above.

See the LabVIEW FPGA 2016 help: http://zone.ni.com/reference/en-XX/help/371599M-01/lvfpgadialog/fpga_data_type_db/

See:

  • Custom Control—Opens a dialog box in which you can navigate to the custom control you want to use. This button appears only when you select Custom Control in the Data Type pull-down menu.

See image below:

FIFO_Custom_Control.png


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
0 Kudos
Message 8 of 8
(2,846 Views)