FPGA Read/Write Control for Multiple VI Options

[toranilor]

Hello,

I am writing a data gathering / processing VI that uses one of two pre-compiled FPGA bitfiles, which is selected via a case selector at the beginning of execution. One of the bitfiles uses a front-panel array to receive instructions, and the other reads them via a DMA FIFO. For the array bitfile, the instructions are sent via a read/write method control. However, because this array is missing from the DMA bitifle, when I wire both bit files as possibilities in a case selector, the read/write method returns an error because the front panel object does not exist for both bitfiles (quite understandably).

Is there any way to configure a read/write control that adapts to the available front-panel items of the loaded VI? In effect, I want to ignore missing front panel variables if they are requested in the read/write method but do not exist in the particular bitfile. This way I can toggle between the methods on startup.

Regards

[GerdW · Accepted solution]

Hi toranilor,

No, the RT host VI will not automatically/magically adapt to the FPGA bitfile…

When you want to call two different FPGA bitfiles from the same RT host VI then both bitfiles need to have the same "frontpanel" (using the same controls in their frontpanel and supporting the same FIFOs).

[toranilor]

Hey GerdW,

I thought that might be the case. I have implemented identical front panels (just dummy arrays for the DMA program) and it functions just fine.

Cheers!