FPGA digital output and analog input synchronize

[iseven]

Hi everyone,

I want to synchronize a digital output and an analog input. So far, I know how to implement flat sequence - and I can synchronize my digital output sequences. What I am trying to do is, during one of those digital output (let's define that as signal C), I want to read from an analog signal. And that read needs to happen while C is on.

With my current setup, I think the analog read would start at the time I want, but I want it to finish when I want as well. And I would need to read the data within 1 micro second too. 

Another issue is how do I continuously run this loops and keep reading the data and saving it to the FPGA? I know that with FIFO, it saves them in FPGA, but I may need millions of data. In that case, I need to transfer the data to the computer when the FPGA memory is nearly full. How do I do that?

Additional info:

I am using USB-7855R. I tied the getting started example, but it only has a vi where it actually have example for analog input. I can also make sync digital outputs as well as reading analog output. But I need to sync the analog reading with the digital outputs. 

Thanks in advance!

[Jacobson-ni]

To answer your second question, the DMA FIFO on the FPGA side is really just temporary storage until the DMA engine can transfer that data to your host.  When you start acquiring data and adding it to your FIFO you will be able to monitor the elements in you host side buffer and read them as necessary.

If you are running out of space on your FIFOs FPGA side buffer then you are likely out of space on your host side buffer (possibly just higher instantaneous bandwidth than what that size buffer can handle).  Your host side buffer can be much much larger so if you are running out of space there you need to be reading faster or more samples per read.