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LVFPGA: Changing trigger level on FlexRIO device TRIG IN

Hi,

 

I have a PXIE-5774 digitizer FPGA-module. I have been using the TRIG IN channel of the FPGA in LabVIEW FPGA to give me true when the trigger triggers. My problem is that the trigger signal needs to be crossing zero (low needs to be negative and high positive) and that is not optimal for my needs. The block diagram of the PXIE-5774 on the trigger part looks like this:

IhmeKyselij_0-1696515912155.png

I am not familiar with circuit diagrams but to my understanding I should be able to change the threshold DAC signal so that it will trigger when crossing to for example 1V. So I could have my trigger signal to be for example 0V low and 2V high. 

Is there a way to do that on LabVIEW FPGA?

I tried The "FPGA I/O method node" but it has no methods and the "FPGA I/O property node" has no properties for the "IO socket/TriggerIn".

 

All help is appreciated!

Aarni

 

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If you build a template project using the shipping example

ZYOng_0-1696551037340.png

 

The example host allows you to configure the trigger level.

ZYOng_1-1696551111690.png

 

The implementation can be found in the DefaultPersonality

ZYOng_2-1696551246398.png

 

ZYOng_3-1696551321841.png

 

 

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Control Lead | Intelline Inc
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